{"id":"https://openalex.org/W2168670003","doi":"https://doi.org/10.1109/icvd.2004.1260984","title":"Fast, layout-aware validation of test-vectors for nanometer-related timing failures","display_name":"Fast, layout-aware validation of test-vectors for nanometer-related timing failures","publication_year":2004,"publication_date":"2004-06-21","ids":{"openalex":"https://openalex.org/W2168670003","doi":"https://doi.org/10.1109/icvd.2004.1260984","mag":"2168670003"},"language":"en","primary_location":{"id":"doi:10.1109/icvd.2004.1260984","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icvd.2004.1260984","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"17th International Conference on VLSI Design. Proceedings.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5058847234","display_name":"A. Kokrady","orcid":null},"institutions":[{"id":"https://openalex.org/I74760111","display_name":"Texas Instruments (United States)","ror":"https://ror.org/03vsmv677","country_code":"US","type":"company","lineage":["https://openalex.org/I74760111"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"A. Kokrady","raw_affiliation_strings":["ASIC Product Development Center, Texas Instruments (India) Private Limited, Bangalore, India"],"affiliations":[{"raw_affiliation_string":"ASIC Product Development Center, Texas Instruments (India) Private Limited, Bangalore, India","institution_ids":["https://openalex.org/I74760111"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5036733255","display_name":"C.P. Ravikumar","orcid":"https://orcid.org/0000-0003-0809-5545"},"institutions":[{"id":"https://openalex.org/I74760111","display_name":"Texas Instruments (United States)","ror":"https://ror.org/03vsmv677","country_code":"US","type":"company","lineage":["https://openalex.org/I74760111"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"C.P. Ravikumar","raw_affiliation_strings":["ASIC Product Development Center, Texas Instruments (India) Private Limited, Bangalore, India"],"affiliations":[{"raw_affiliation_string":"ASIC Product Development Center, Texas Instruments (India) Private Limited, Bangalore, India","institution_ids":["https://openalex.org/I74760111"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5058847234"],"corresponding_institution_ids":["https://openalex.org/I74760111"],"apc_list":null,"apc_paid":null,"fwci":2.8963,"has_fulltext":false,"cited_by_count":28,"citation_normalized_percentile":{"value":0.90656401,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"597","last_page":"602"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.6902125477790833},{"id":"https://openalex.org/keywords/correctness","display_name":"Correctness","score":0.6597565412521362},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.53298419713974},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5170691609382629},{"id":"https://openalex.org/keywords/built-in-self-test","display_name":"Built-in self-test","score":0.4937632977962494},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.49039459228515625},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.46931907534599304},{"id":"https://openalex.org/keywords/test-compression","display_name":"Test compression","score":0.4650472402572632},{"id":"https://openalex.org/keywords/device-under-test","display_name":"Device under test","score":0.44486504793167114},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.43815380334854126},{"id":"https://openalex.org/keywords/process-corners","display_name":"Process corners","score":0.4296817481517792},{"id":"https://openalex.org/keywords/signal-integrity","display_name":"Signal integrity","score":0.42748844623565674},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.42162346839904785},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.3649042248725891},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3484976887702942},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.2688955068588257},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.2655297517776489},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.23138397932052612},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.19901156425476074},{"id":"https://openalex.org/keywords/printed-circuit-board","display_name":"Printed circuit board","score":0.17441272735595703}],"concepts":[{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.6902125477790833},{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.6597565412521362},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.53298419713974},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5170691609382629},{"id":"https://openalex.org/C2780980493","wikidata":"https://www.wikidata.org/wiki/Q181142","display_name":"Built-in self-test","level":2,"score":0.4937632977962494},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.49039459228515625},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.46931907534599304},{"id":"https://openalex.org/C29652920","wikidata":"https://www.wikidata.org/wiki/Q7705757","display_name":"Test compression","level":4,"score":0.4650472402572632},{"id":"https://openalex.org/C76249512","wikidata":"https://www.wikidata.org/wiki/Q1206780","display_name":"Device under test","level":3,"score":0.44486504793167114},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.43815380334854126},{"id":"https://openalex.org/C192615534","wikidata":"https://www.wikidata.org/wiki/Q7247268","display_name":"Process corners","level":3,"score":0.4296817481517792},{"id":"https://openalex.org/C44938667","wikidata":"https://www.wikidata.org/wiki/Q4503810","display_name":"Signal integrity","level":3,"score":0.42748844623565674},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.42162346839904785},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.3649042248725891},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3484976887702942},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.2688955068588257},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.2655297517776489},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.23138397932052612},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.19901156425476074},{"id":"https://openalex.org/C120793396","wikidata":"https://www.wikidata.org/wiki/Q173350","display_name":"Printed circuit board","level":2,"score":0.17441272735595703},{"id":"https://openalex.org/C195266298","wikidata":"https://www.wikidata.org/wiki/Q2165620","display_name":"Scattering parameters","level":2,"score":0.0},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icvd.2004.1260984","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icvd.2004.1260984","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"17th International Conference on VLSI Design. Proceedings.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1595368737","https://openalex.org/W1970793581","https://openalex.org/W2003379369","https://openalex.org/W2105954189","https://openalex.org/W2108879261","https://openalex.org/W2111253307","https://openalex.org/W2125366029","https://openalex.org/W2146379415","https://openalex.org/W6635424516"],"related_works":["https://openalex.org/W4245311057","https://openalex.org/W311918050","https://openalex.org/W2061326683","https://openalex.org/W2543176856","https://openalex.org/W2165948443","https://openalex.org/W2550015578","https://openalex.org/W2377850316","https://openalex.org/W2167255265","https://openalex.org/W2146381271","https://openalex.org/W2989178840"],"abstract_inverted_index":{"ATPG":[0],"tools":[1],"generate":[2],"test":[3,43,64,76,79,114,197,252,256,298],"vectors":[4,48,65,253,257,299],"assuming":[5],"the":[6,47,58,72,75,96,104,111,152,179,200,208,217,230,241,244,273,297],"zero":[7],"delay":[8,133,164],"model":[9],"for":[10,49,138],"logic":[11],"gates.":[12],"In":[13],"reality,":[14],"however,":[15],"gates":[16],"have":[17],"finite":[18],"rise":[19],"and":[20,29,38,91,99,131,173,202,254],"fall":[21],"delays":[22],"that":[23,198,258],"are":[24,54,135,283],"dependent":[25],"on":[26,35,307],"process,":[27],"voltage,":[28],"temperature":[30],"variations":[31],"across":[32],"different":[33],"dies":[34],"a":[36,40,89,92,177,183,193,196,292],"wafer":[37],"within":[39],"die.":[41],"A":[42,78],"engineer":[44],"must":[45],"verify":[46],"timing":[50],"correctness":[51],"before":[52],"they":[53,161],"handed":[55],"off":[56],"to":[57,113,167,189,222,226,264,295,300,313],"product":[59],"engineer.":[60],"Currently,":[61],"validation":[62,180],"of":[63,71,103,120,195,243,250,275,287],"is":[66,81,156,192,225],"done":[67],"using":[68,74],"dynamic":[69,184,269],"simulation":[70,185,270,277,280],"circuit":[73,94,153,276],"vectors.":[77],"vector":[80],"invalidated":[82],"if":[83],"it":[84,204],"cannot":[85],"reliably":[86],"distinguish":[87],"between":[88],"good":[90],"faulty":[93,205],"under":[95],"signal":[97],"placement":[98],"observation":[100],"error":[101],"window":[102],"tester":[105],"equipment.":[106],"As":[107,176],"chips":[108],"become":[109],"faster,":[110],"need":[112],"them":[115],"at":[116,216],"their":[117],"intended":[118,218],"speed":[119],"operation":[121],"has":[122],"been":[123],"recognized;":[124],"accordingly,":[125],"at-speed":[126,251],"functional":[127,214],"tests,":[128],"memory":[129],"BIST,":[130],"transition":[132],"tests":[134,143],"being":[136],"used":[137],"modern":[139],"ASICs.":[140],"Since":[141],"structural":[142],"can":[144,186,259],"result":[145,260],"in":[146,151,213,261,268,285],"much":[147],"more":[148],"switching":[149],"activity":[150],"than":[154],"what":[155],"estimated":[157],"during":[158],"normal":[159],"functioning,":[160],"may":[162,210],"fail":[163],"testing":[165],"due":[166],"nanometer":[168],"effects":[169],"such":[170],"as":[171],"crosstalk":[172],"IR":[174],"drop.":[175],"result,":[178],"performed":[181],"by":[182],"be":[187,311],"prone":[188],"error.":[190],"Here":[191],"case":[194],"over-exercises":[199],"chip":[201,209],"declares":[203],"even":[206],"when":[207],"work":[211],"correctly":[212],"mode":[215],"speed.":[219],"One":[220],"solution":[221],"this":[223,238,266],"problem":[224],"overdesign,":[227],"e.g.":[228],"oversize":[229],"power":[231],"rails":[232],"or":[233,278],"increase":[234],"wiring":[235],"pitch,":[236],"but":[237],"will":[239,271,310],"impact":[240],"yield":[242],"product.":[245],"We":[246,290],"propose":[247],"layout-aware":[248],"verification":[249,267],"eliminating":[255],"misclassification.":[262],"Attempting":[263],"address":[265],"force":[272],"use":[274],"mixed-level":[279],"techniques,":[281],"which":[282],"expensive":[284],"terms":[286],"run":[288],"time.":[289,304],"discuss":[291],"static":[293],"approach":[294],"validate":[296],"save":[301],"valuable":[302],"cycle":[303],"Experimental":[305],"results":[306],"two":[308],"designs":[309],"presented":[312],"illustrate":[314],"our":[315],"approach.":[316]},"counts_by_year":[{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}