{"id":"https://openalex.org/W2134925363","doi":"https://doi.org/10.1109/icvd.2004.1260982","title":"Can SAT be used to improve sequential ATPG methods?","display_name":"Can SAT be used to improve sequential ATPG methods?","publication_year":2004,"publication_date":"2004-06-21","ids":{"openalex":"https://openalex.org/W2134925363","doi":"https://doi.org/10.1109/icvd.2004.1260982","mag":"2134925363"},"language":"en","primary_location":{"id":"doi:10.1109/icvd.2004.1260982","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icvd.2004.1260982","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"17th International Conference on VLSI Design. Proceedings.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101870966","display_name":"Mukul R. Prasad","orcid":null},"institutions":[{"id":"https://openalex.org/I4210094759","display_name":"Fujitsu (United States)","ror":"https://ror.org/0073whr05","country_code":"US","type":"company","lineage":["https://openalex.org/I2252096349","https://openalex.org/I4210094759"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M.R. Prasad","raw_affiliation_strings":["Fujitsu Laboratories of America, Inc., Sunnyvale, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Fujitsu Laboratories of America, Inc., Sunnyvale, CA, USA","institution_ids":["https://openalex.org/I4210094759"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5045190420","display_name":"Ming-Jun Hsiao","orcid":null},"institutions":[{"id":"https://openalex.org/I859038795","display_name":"Virginia Tech","ror":"https://ror.org/02smfhw86","country_code":"US","type":"education","lineage":["https://openalex.org/I859038795"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M.S. Hsiao","raw_affiliation_strings":["Bradley Department of Electrical & Computer Engineering, Virginia Technology, Blacksburg, VA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Bradley Department of Electrical & Computer Engineering, Virginia Technology, Blacksburg, VA, USA","institution_ids":["https://openalex.org/I859038795"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5083173943","display_name":"J. Jain","orcid":"https://orcid.org/0009-0001-1196-0643"},"institutions":[{"id":"https://openalex.org/I4210094759","display_name":"Fujitsu (United States)","ror":"https://ror.org/0073whr05","country_code":"US","type":"company","lineage":["https://openalex.org/I2252096349","https://openalex.org/I4210094759"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J. Jain","raw_affiliation_strings":["Fujitsu Laboratories of America, Inc., Sunnyvale, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Fujitsu Laboratories of America, Inc., Sunnyvale, CA, USA","institution_ids":["https://openalex.org/I4210094759"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.0383,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.78174175,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":"1954","issue":null,"first_page":"585","last_page":"590"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10743","display_name":"Software Testing and Debugging Techniques","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/1712","display_name":"Software"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9915000200271606,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.8724350929260254},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6978518962860107},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.4566967785358429},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4341311752796173},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3959174156188965},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3954348564147949},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.36144182085990906},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.28351184725761414},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14652284979820251},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.09151411056518555}],"concepts":[{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.8724350929260254},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6978518962860107},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.4566967785358429},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4341311752796173},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3959174156188965},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3954348564147949},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.36144182085990906},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.28351184725761414},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14652284979820251},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.09151411056518555},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icvd.2004.1260982","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icvd.2004.1260982","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"17th International Conference on VLSI Design. Proceedings.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":54,"referenced_works":["https://openalex.org/W1493721853","https://openalex.org/W1494481937","https://openalex.org/W1495266209","https://openalex.org/W1511155470","https://openalex.org/W1555280138","https://openalex.org/W1787074469","https://openalex.org/W1838320025","https://openalex.org/W1903629970","https://openalex.org/W2019642743","https://openalex.org/W2025911519","https://openalex.org/W2044560939","https://openalex.org/W2069560114","https://openalex.org/W2075959177","https://openalex.org/W2078866600","https://openalex.org/W2100404896","https://openalex.org/W2103375392","https://openalex.org/W2107470986","https://openalex.org/W2118346508","https://openalex.org/W2122600622","https://openalex.org/W2129369779","https://openalex.org/W2133211121","https://openalex.org/W2135613306","https://openalex.org/W2135931142","https://openalex.org/W2139171217","https://openalex.org/W2142785340","https://openalex.org/W2143744297","https://openalex.org/W2146662253","https://openalex.org/W2153702325","https://openalex.org/W2158966008","https://openalex.org/W2160444875","https://openalex.org/W2161157457","https://openalex.org/W2162116017","https://openalex.org/W2168081446","https://openalex.org/W2170795408","https://openalex.org/W3045969830","https://openalex.org/W3149357776","https://openalex.org/W4230587734","https://openalex.org/W4231640108","https://openalex.org/W4236423066","https://openalex.org/W4239219002","https://openalex.org/W4241530675","https://openalex.org/W4247585869","https://openalex.org/W4252315883","https://openalex.org/W6629484655","https://openalex.org/W6629648295","https://openalex.org/W6630643794","https://openalex.org/W6633364034","https://openalex.org/W6638020115","https://openalex.org/W6670691266","https://openalex.org/W6674923524","https://openalex.org/W6676112844","https://openalex.org/W6677600375","https://openalex.org/W6679299262","https://openalex.org/W6683308379"],"related_works":["https://openalex.org/W2134454856","https://openalex.org/W4245485844","https://openalex.org/W2006457427","https://openalex.org/W1969142133","https://openalex.org/W2141396628","https://openalex.org/W2120257283","https://openalex.org/W2105463797","https://openalex.org/W2137555930","https://openalex.org/W4239219002","https://openalex.org/W1995481531"],"abstract_inverted_index":{"In":[0],"this":[1],"work":[2],"we":[3],"investigate":[4],"the":[5,18,22],"integration":[6],"of":[7,20,32],"SAT":[8],"methods":[9],"into":[10],"a":[11,29],"simulation-based":[12],"sequential":[13,25],"ATPG":[14],"tool,":[15],"STRATEGATE,":[16],"with":[17],"aim":[19],"improving":[21],"state-of-the-art":[23],"in":[24],"ATPG.":[26],"We":[27],"offer":[28],"detailed":[30],"analysis":[31],"possible":[33],"scenarios":[34],"and":[35],"algorithms":[36],"for":[37],"performing":[38],"such":[39,47],"an":[40],"integration.":[41],"Our":[42],"preliminary":[43],"investigations":[44],"show":[45],"that":[46],"hybrid":[48],"approaches":[49],"can":[50],"be":[51],"very":[52],"promising.":[53]},"counts_by_year":[{"year":2015,"cited_by_count":2},{"year":2012,"cited_by_count":2}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
