{"id":"https://openalex.org/W2112259817","doi":"https://doi.org/10.1109/icvd.2004.1260972","title":"Multiprocessor architectures for embedded system-on-chip applications","display_name":"Multiprocessor architectures for embedded system-on-chip applications","publication_year":2004,"publication_date":"2004-06-21","ids":{"openalex":"https://openalex.org/W2112259817","doi":"https://doi.org/10.1109/icvd.2004.1260972","mag":"2112259817"},"language":"en","primary_location":{"id":"doi:10.1109/icvd.2004.1260972","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icvd.2004.1260972","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"17th International Conference on VLSI Design. Proceedings.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5036733255","display_name":"C.P. Ravikumar","orcid":"https://orcid.org/0000-0003-0809-5545"},"institutions":[{"id":"https://openalex.org/I4210109535","display_name":"Texas Instruments (India)","ror":"https://ror.org/01t305n31","country_code":"IN","type":"company","lineage":["https://openalex.org/I4210109535","https://openalex.org/I74760111"]},{"id":"https://openalex.org/I74760111","display_name":"Texas Instruments (United States)","ror":"https://ror.org/03vsmv677","country_code":"US","type":"company","lineage":["https://openalex.org/I74760111"]}],"countries":["IN","US"],"is_corresponding":true,"raw_author_name":"C.P. Ravikumar","raw_affiliation_strings":["Texas Instruments (India) Private Limited, Bangalore, India","Texas Instrum., Bangalore, India"],"affiliations":[{"raw_affiliation_string":"Texas Instruments (India) Private Limited, Bangalore, India","institution_ids":["https://openalex.org/I4210109535"]},{"raw_affiliation_string":"Texas Instrum., Bangalore, India","institution_ids":["https://openalex.org/I74760111"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5036733255"],"corresponding_institution_ids":["https://openalex.org/I4210109535","https://openalex.org/I74760111"],"apc_list":null,"apc_paid":null,"fwci":1.3905,"has_fulltext":false,"cited_by_count":19,"citation_normalized_percentile":{"value":0.85154688,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":95},"biblio":{"volume":"q2","issue":null,"first_page":"512","last_page":"519"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/uniprocessor-system","display_name":"Uniprocessor system","score":0.8933942914009094},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8551838397979736},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.7740058898925781},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5503331422805786},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5371637344360352},{"id":"https://openalex.org/keywords/symmetric-multiprocessor-system","display_name":"Symmetric multiprocessor system","score":0.4908984303474426},{"id":"https://openalex.org/keywords/video-processing","display_name":"Video processing","score":0.45209556818008423},{"id":"https://openalex.org/keywords/graphics","display_name":"Graphics","score":0.4492935240268707},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.4327477812767029},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.2810917794704437},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.24086177349090576},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.22476419806480408}],"concepts":[{"id":"https://openalex.org/C79189994","wikidata":"https://www.wikidata.org/wiki/Q3488021","display_name":"Uniprocessor system","level":3,"score":0.8933942914009094},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8551838397979736},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.7740058898925781},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5503331422805786},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5371637344360352},{"id":"https://openalex.org/C172430144","wikidata":"https://www.wikidata.org/wiki/Q17111997","display_name":"Symmetric multiprocessor system","level":2,"score":0.4908984303474426},{"id":"https://openalex.org/C65483669","wikidata":"https://www.wikidata.org/wiki/Q3536669","display_name":"Video processing","level":2,"score":0.45209556818008423},{"id":"https://openalex.org/C21442007","wikidata":"https://www.wikidata.org/wiki/Q1027879","display_name":"Graphics","level":2,"score":0.4492935240268707},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.4327477812767029},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.2810917794704437},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.24086177349090576},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.22476419806480408}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icvd.2004.1260972","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icvd.2004.1260972","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"17th International Conference on VLSI Design. Proceedings.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":31,"referenced_works":["https://openalex.org/W79098930","https://openalex.org/W1508451093","https://openalex.org/W1510738892","https://openalex.org/W1555915743","https://openalex.org/W1918487774","https://openalex.org/W1971851724","https://openalex.org/W2002554499","https://openalex.org/W2036523152","https://openalex.org/W2054732504","https://openalex.org/W2090242529","https://openalex.org/W2095006208","https://openalex.org/W2110333324","https://openalex.org/W2111867711","https://openalex.org/W2119677480","https://openalex.org/W2122781161","https://openalex.org/W2123502138","https://openalex.org/W2124313718","https://openalex.org/W2133408285","https://openalex.org/W2145163878","https://openalex.org/W2159132435","https://openalex.org/W2167240608","https://openalex.org/W2171825402","https://openalex.org/W4233673249","https://openalex.org/W4245982457","https://openalex.org/W4251593014","https://openalex.org/W4256282209","https://openalex.org/W6640092377","https://openalex.org/W6673944427","https://openalex.org/W6678040605","https://openalex.org/W6680057268","https://openalex.org/W6683580681"],"related_works":["https://openalex.org/W2186708011","https://openalex.org/W2134237474","https://openalex.org/W2109868689","https://openalex.org/W2899110000","https://openalex.org/W2039391036","https://openalex.org/W2021050177","https://openalex.org/W232296991","https://openalex.org/W2105876736","https://openalex.org/W2106200299","https://openalex.org/W2285316324"],"abstract_inverted_index":{"Real-time":[0],"multimedia":[1],"applications":[2],"that":[3,52,84,93],"involve":[4],"processing":[5,68],"of":[6,14,81],"video":[7],"and":[8,41,67],"audio":[9],"streams":[10],"demand":[11],"computational":[12],"performance":[13],"a":[15,26,56,112],"few":[16],"Giga":[17],"operations":[18],"per":[19],"second,":[20],"which":[21,44],"cannot":[22],"be":[23,63],"obtained":[24],"using":[25],"single":[27],"processor.":[28,58],"An":[29],"embedded":[30,89],"system":[31],"intended":[32],"for":[33,65,87,105],"such":[34,88,111],"an":[35,79,101,119],"application":[36,108],"must":[37],"also":[38,62],"support":[39],"networking":[40],"IO":[42],"interfaces,":[43],"are":[45,53,85],"best":[46],"handled":[47],"by":[48,55],"dedicated":[49],"interface":[50],"processors":[51,60],"coordinated":[54],"housekeeping":[57],"Dedicated":[59],"may":[61,109],"necessary":[64],"parsing":[66],"video/audio":[69],"stream":[70],"and,":[71],"video/graphics":[72],"rendering.":[73],"In":[74],"this":[75],"paper,":[76],"we":[77],"provide":[78],"overview":[80],"multiprocessor":[82,117],"architectures":[83],"evolving":[86],"applications.":[90],"We":[91],"argue":[92],"the":[94,106],"VLSI":[95],"design":[96],"challenges":[97],"involved":[98],"in":[99],"designing":[100],"equivalent":[102],"uniprocessor":[103],"solution":[104,113],"same":[107],"make":[110],"prohibitively":[114],"expensive,":[115],"making":[116],"SoC":[118],"attractive":[120],"alternative.":[121]},"counts_by_year":[{"year":2021,"cited_by_count":2},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}