{"id":"https://openalex.org/W2117998167","doi":"https://doi.org/10.1109/icvd.2004.1260933","title":"An ILP formulation for system level throughput and power optimization in multiprocessor SoC architectures","display_name":"An ILP formulation for system level throughput and power optimization in multiprocessor SoC architectures","publication_year":2004,"publication_date":"2004-06-03","ids":{"openalex":"https://openalex.org/W2117998167","doi":"https://doi.org/10.1109/icvd.2004.1260933","mag":"2117998167"},"language":"en","primary_location":{"id":"doi:10.1109/icvd.2004.1260933","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icvd.2004.1260933","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. 17th International Conference on VLSI Design","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5110252193","display_name":"K. Srinivasan","orcid":null},"institutions":[{"id":"https://openalex.org/I55732556","display_name":"Arizona State University","ror":"https://ror.org/03efmqc40","country_code":"US","type":"education","lineage":["https://openalex.org/I55732556"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"K. Srinivasan","raw_affiliation_strings":["Department of Computer Science and Engineering, Arizona State University, Tempe, AZ, USA","Department of Computer Science & Engineering, Arizona State University, Tempe, AZ, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Arizona State University, Tempe, AZ, USA","institution_ids":["https://openalex.org/I55732556"]},{"raw_affiliation_string":"Department of Computer Science & Engineering, Arizona State University, Tempe, AZ, USA","institution_ids":["https://openalex.org/I55732556"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5109416106","display_name":"Karam S. Chatha","orcid":null},"institutions":[{"id":"https://openalex.org/I55732556","display_name":"Arizona State University","ror":"https://ror.org/03efmqc40","country_code":"US","type":"education","lineage":["https://openalex.org/I55732556"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"K.S. Chatha","raw_affiliation_strings":["Department of Computer Science and Engineering, Arizona State University, Tempe, AZ, USA","Department of Computer Science & Engineering, Arizona State University, Tempe, AZ, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Arizona State University, Tempe, AZ, USA","institution_ids":["https://openalex.org/I55732556"]},{"raw_affiliation_string":"Department of Computer Science & Engineering, Arizona State University, Tempe, AZ, USA","institution_ids":["https://openalex.org/I55732556"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I55732556"],"apc_list":null,"apc_paid":null,"fwci":0.618,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.61762742,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"255","last_page":"260"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7403509020805359},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.72019362449646},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6932531595230103},{"id":"https://openalex.org/keywords/loop-unrolling","display_name":"Loop unrolling","score":0.6131290793418884},{"id":"https://openalex.org/keywords/integer-programming","display_name":"Integer programming","score":0.6109515428543091},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.5605108737945557},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.5398134589195251},{"id":"https://openalex.org/keywords/linear-programming","display_name":"Linear programming","score":0.5257048010826111},{"id":"https://openalex.org/keywords/dynamic-voltage-scaling","display_name":"Dynamic voltage scaling","score":0.517989993095398},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4200414717197418},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.41367167234420776},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.33377355337142944},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.23473027348518372},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.17130109667778015},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.12739112973213196}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7403509020805359},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.72019362449646},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6932531595230103},{"id":"https://openalex.org/C76970557","wikidata":"https://www.wikidata.org/wiki/Q1869750","display_name":"Loop unrolling","level":3,"score":0.6131290793418884},{"id":"https://openalex.org/C56086750","wikidata":"https://www.wikidata.org/wiki/Q6042592","display_name":"Integer programming","level":2,"score":0.6109515428543091},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5605108737945557},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5398134589195251},{"id":"https://openalex.org/C41045048","wikidata":"https://www.wikidata.org/wiki/Q202843","display_name":"Linear programming","level":2,"score":0.5257048010826111},{"id":"https://openalex.org/C2776047111","wikidata":"https://www.wikidata.org/wiki/Q632037","display_name":"Dynamic voltage scaling","level":3,"score":0.517989993095398},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4200414717197418},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.41367167234420776},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.33377355337142944},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.23473027348518372},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.17130109667778015},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.12739112973213196},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icvd.2004.1260933","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icvd.2004.1260933","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. 17th International Conference on VLSI Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8899999856948853,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":25,"referenced_works":["https://openalex.org/W1531850176","https://openalex.org/W1999640823","https://openalex.org/W2006075719","https://openalex.org/W2026958591","https://openalex.org/W2078308569","https://openalex.org/W2104865575","https://openalex.org/W2106292145","https://openalex.org/W2109093878","https://openalex.org/W2136244995","https://openalex.org/W2136982937","https://openalex.org/W2138625816","https://openalex.org/W2145219443","https://openalex.org/W2146828012","https://openalex.org/W2152951583","https://openalex.org/W2167625280","https://openalex.org/W2752885492","https://openalex.org/W3019365222","https://openalex.org/W3145128584","https://openalex.org/W4235090510","https://openalex.org/W4238849053","https://openalex.org/W6631692153","https://openalex.org/W6676031445","https://openalex.org/W6676281777","https://openalex.org/W6681274207","https://openalex.org/W7029321148"],"related_works":["https://openalex.org/W2148967747","https://openalex.org/W4256534760","https://openalex.org/W3008658471","https://openalex.org/W2133860611","https://openalex.org/W1986517065","https://openalex.org/W2996717348","https://openalex.org/W2383384613","https://openalex.org/W2120080222","https://openalex.org/W2801267242","https://openalex.org/W2055261421"],"abstract_inverted_index":{"System-level":[0],"low":[1,44],"power":[2,12,45,53,59,120],"scheduling":[3],"techniques":[4,47],"are":[5,17,108],"required":[6],"for":[7],"optimizing":[8],"the":[9,58,63,69,83,99,144],"performance":[10],"and":[11,40,42,52,65,138],"of":[13,68],"embedded":[14],"applications":[15],"that":[16,35,76],"mapped":[18],"to":[19,56,88],"multiprocessor":[20],"System-on-Chip":[21],"(SoC)":[22],"architectures.":[23],"In":[24],"this":[25],"paper,":[26],"we":[27],"present":[28,73,94],"an":[29,102],"integer":[30],"linear":[31,141],"programming":[32],"(ILP)":[33],"formulation":[34,85],"combines":[36],"loop":[37],"transformations":[38],"(pipelining":[39],"unrolling)":[41],"system-level":[43,119],"optimization":[46],"(dynamic":[48],"voltage":[49],"scaling":[50],"(DVS)":[51],"management":[54],"(DPM))":[55],"minimize":[57],"consumption,":[60],"while":[61],"satisfying":[62],"period":[64],"deadline":[66],"constraints":[67,81],"application.":[70],"We":[71,93],"also":[72],"three":[74],"modifications":[75],"relax":[77],"one":[78],"or":[79],"more":[80],"in":[82,86,117,133,136,143],"optimal":[84],"order":[87],"obtain":[89],"smaller":[90],"run":[91],"times.":[92],"experimental":[95],"analysis":[96],"by":[97],"applying":[98],"formulations":[100,115,131],"on":[101],"MPEG":[103],"decoder":[104],"algorithm.":[105],"All":[106],"results":[107],"compared":[109],"against":[110],"two":[111],"existing":[112],"techniques.":[113],"Our":[114],"result":[116,132,145],"large":[118],"reductions":[121],"(max:":[122],"48.2%,":[123],"min:":[124],"15.92%,":[125],"avg:":[126],"31.9%).":[127],"The":[128],"modified":[129],"ILP":[130],"exponential":[134],"decrease":[135],"runtimes,":[137],"a":[139],"corresponding":[140],"degradation":[142],"quality.":[146]},"counts_by_year":[{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
