{"id":"https://openalex.org/W2109600042","doi":"https://doi.org/10.1109/icvd.2004.1260927","title":"Leakage reduction techniques in a 0.13 um SRAM cell","display_name":"Leakage reduction techniques in a 0.13 um SRAM cell","publication_year":2004,"publication_date":"2004-06-30","ids":{"openalex":"https://openalex.org/W2109600042","doi":"https://doi.org/10.1109/icvd.2004.1260927","mag":"2109600042"},"language":"en","primary_location":{"id":"doi:10.1109/icvd.2004.1260927","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icvd.2004.1260927","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"17th International Conference on VLSI Design. Proceedings.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5011205716","display_name":"S. Romanovsky","orcid":null},"institutions":[{"id":"https://openalex.org/I4210159148","display_name":"Ansys (Canada)","ror":"https://ror.org/04kdd0e80","country_code":"CA","type":"company","lineage":["https://openalex.org/I21160419","https://openalex.org/I4210159148"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"S. Romanovsky","raw_affiliation_strings":["MoSys, Inc.orporated, Kanata, ONT, Canada","MoSys Inc., Kanata, Ont., Canada"],"affiliations":[{"raw_affiliation_string":"MoSys, Inc.orporated, Kanata, ONT, Canada","institution_ids":[]},{"raw_affiliation_string":"MoSys Inc., Kanata, Ont., Canada","institution_ids":["https://openalex.org/I4210159148"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5004905159","display_name":"Arun Achyuthan","orcid":null},"institutions":[{"id":"https://openalex.org/I4210159148","display_name":"Ansys (Canada)","ror":"https://ror.org/04kdd0e80","country_code":"CA","type":"company","lineage":["https://openalex.org/I21160419","https://openalex.org/I4210159148"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"A. Achyuthan","raw_affiliation_strings":["MoSys, Inc.orporated, Kanata, ONT, Canada","MoSys Inc., Kanata, Ont., Canada"],"affiliations":[{"raw_affiliation_string":"MoSys, Inc.orporated, Kanata, ONT, Canada","institution_ids":[]},{"raw_affiliation_string":"MoSys Inc., Kanata, Ont., Canada","institution_ids":["https://openalex.org/I4210159148"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108704688","display_name":"S. Natarajan","orcid":null},"institutions":[{"id":"https://openalex.org/I4210159148","display_name":"Ansys (Canada)","ror":"https://ror.org/04kdd0e80","country_code":"CA","type":"company","lineage":["https://openalex.org/I21160419","https://openalex.org/I4210159148"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"S. Natarajan","raw_affiliation_strings":["MoSys, Inc.orporated, Kanata, ONT, Canada","MoSys Inc., Kanata, Ont., Canada"],"affiliations":[{"raw_affiliation_string":"MoSys, Inc.orporated, Kanata, ONT, Canada","institution_ids":[]},{"raw_affiliation_string":"MoSys Inc., Kanata, Ont., Canada","institution_ids":["https://openalex.org/I4210159148"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5108321154","display_name":"Wing Yan Leung","orcid":"https://orcid.org/0009-0006-4387-2556"},"institutions":[{"id":"https://openalex.org/I4210159148","display_name":"Ansys (Canada)","ror":"https://ror.org/04kdd0e80","country_code":"CA","type":"company","lineage":["https://openalex.org/I21160419","https://openalex.org/I4210159148"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Wing Leung","raw_affiliation_strings":["MoSys, Inc.orporated, Kanata, ONT, Canada","MoSys Inc., Kanata, Ont., Canada"],"affiliations":[{"raw_affiliation_string":"MoSys, Inc.orporated, Kanata, ONT, Canada","institution_ids":[]},{"raw_affiliation_string":"MoSys Inc., Kanata, Ont., Canada","institution_ids":["https://openalex.org/I4210159148"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5011205716"],"corresponding_institution_ids":["https://openalex.org/I4210159148"],"apc_list":null,"apc_paid":null,"fwci":0.3292,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.64393285,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"215","last_page":"221"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.8649741411209106},{"id":"https://openalex.org/keywords/leakage","display_name":"Leakage (economics)","score":0.8031659126281738},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.6697579026222229},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.6289098858833313},{"id":"https://openalex.org/keywords/noise-margin","display_name":"Noise margin","score":0.5464091300964355},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5214454531669617},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4709632992744446},{"id":"https://openalex.org/keywords/standby-power","display_name":"Standby power","score":0.450999915599823},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.4481373429298401},{"id":"https://openalex.org/keywords/process-corners","display_name":"Process corners","score":0.4383637011051178},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.40825095772743225},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3476219177246094},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.22295957803726196}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.8649741411209106},{"id":"https://openalex.org/C2777042071","wikidata":"https://www.wikidata.org/wiki/Q6509304","display_name":"Leakage (economics)","level":2,"score":0.8031659126281738},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.6697579026222229},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.6289098858833313},{"id":"https://openalex.org/C179499742","wikidata":"https://www.wikidata.org/wiki/Q1324892","display_name":"Noise margin","level":4,"score":0.5464091300964355},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5214454531669617},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4709632992744446},{"id":"https://openalex.org/C7140552","wikidata":"https://www.wikidata.org/wiki/Q1366402","display_name":"Standby power","level":3,"score":0.450999915599823},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.4481373429298401},{"id":"https://openalex.org/C192615534","wikidata":"https://www.wikidata.org/wiki/Q7247268","display_name":"Process corners","level":3,"score":0.4383637011051178},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.40825095772743225},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3476219177246094},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.22295957803726196},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icvd.2004.1260927","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icvd.2004.1260927","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"17th International Conference on VLSI Design. Proceedings.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.4699999988079071,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W2096362780","https://openalex.org/W2109220580","https://openalex.org/W2114226166","https://openalex.org/W2182849795","https://openalex.org/W4243509556","https://openalex.org/W6655446401"],"related_works":["https://openalex.org/W2120398954","https://openalex.org/W2773448237","https://openalex.org/W2119312496","https://openalex.org/W2188598220","https://openalex.org/W4247460323","https://openalex.org/W2162271340","https://openalex.org/W2107909712","https://openalex.org/W2894040387","https://openalex.org/W2537086382","https://openalex.org/W2110253107"],"abstract_inverted_index":{"SRAM":[0,31,136],"standby":[1,54,146],"leakage":[2,24,74,147],"is":[3],"very":[4],"becoming":[5],"critical":[6,135],"with":[7],"technology":[8],"scaling":[9],"to":[10,52,75,88,91,144,151],"meet":[11],"the":[12,23,39,73,96,109,118,122,132,152],"industry's":[13],"demanding":[14],"low":[15],"power":[16],"requirements.":[17],"This":[18,129],"paper":[19,130],"discusses":[20],"some":[21],"of":[22,61,95,134],"reduction":[25],"techniques":[26],"in":[27,33],"a":[28,34],"0.13":[29],"um":[30],"cell":[32,40,137],"standard":[35],"foundry":[36],"process.":[37],"Varying":[38],"bias":[41,63,110,141],"voltages":[42,64,142],"(VDD,":[43],"VSS,":[44],"well":[45],"biases,":[46],"bit-line":[47,84],"pre-charge,":[48],"and":[49,83,121,148],"wordline":[50],"off)":[51],"different":[53,140],"levels":[55,71,86],"helps":[56],"achieve":[57],"reduced":[58],"leakage.":[59],"Variation":[60],"these":[62],"by":[65],"0.3":[66],"v":[67],"from":[68],"normal":[69,97],"voltage":[70,111],"reduces":[72],"10":[76],"pA/Cell":[77],"at":[78,92],"room":[79],"temperature.":[80],"The":[81],"VDD":[82],"pre-charge":[85],"need":[87],"be":[89,127],"restored":[90],"least":[93],"95%":[94],"level":[98],"before":[99],"an":[100],"active":[101],"cycle":[102],"for":[103,139],"reliable":[104],"noise":[105,124],"margin.":[106],"Depending":[107],"on":[108],"(VDD":[112],"or":[113,115],"VSS":[114],"both)":[116],"variation,":[117],"access":[119],"time":[120],"static":[123],"margin":[125],"will":[126],"affected.":[128],"studies":[131],"details":[133],"parameters":[138],"variations":[143],"reduce":[145],"their":[149],"impact":[150],"overall":[153],"design.":[154]},"counts_by_year":[{"year":2016,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}