{"id":"https://openalex.org/W2162610412","doi":"https://doi.org/10.1109/icvd.2004.1260892","title":"High level design validation: current practices and future directions","display_name":"High level design validation: current practices and future directions","publication_year":2004,"publication_date":"2004-06-21","ids":{"openalex":"https://openalex.org/W2162610412","doi":"https://doi.org/10.1109/icvd.2004.1260892","mag":"2162610412"},"language":"en","primary_location":{"id":"doi:10.1109/icvd.2004.1260892","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icvd.2004.1260892","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"17th International Conference on VLSI Design. Proceedings.","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5102001964","display_name":"Indradeep Ghosh","orcid":"https://orcid.org/0000-0003-3146-4003"},"institutions":[{"id":"https://openalex.org/I4210094759","display_name":"Fujitsu (United States)","ror":"https://ror.org/0073whr05","country_code":"US","type":"company","lineage":["https://openalex.org/I2252096349","https://openalex.org/I4210094759"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"I. Ghosh","raw_affiliation_strings":["Fujitsu Laboratories of America, Inc., Sunnyvale, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Fujitsu Laboratories of America, Inc., Sunnyvale, CA, USA","institution_ids":["https://openalex.org/I4210094759"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5069043950","display_name":"Munaga V. N. K. Prasad","orcid":"https://orcid.org/0000-0002-5560-7649"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"M. Prasad","raw_affiliation_strings":["Calypto Design Systems, Inc., Santa Clara, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Calypto Design Systems, Inc., Santa Clara, CA, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5013076039","display_name":"Rajarshi Mukherjee","orcid":"https://orcid.org/0000-0002-5761-8958"},"institutions":[{"id":"https://openalex.org/I4210094759","display_name":"Fujitsu (United States)","ror":"https://ror.org/0073whr05","country_code":"US","type":"company","lineage":["https://openalex.org/I2252096349","https://openalex.org/I4210094759"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"R. Mukherjee","raw_affiliation_strings":["Fujitsu Laboratories of America, Inc., Sunnyvale, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Fujitsu Laboratories of America, Inc., Sunnyvale, CA, USA","institution_ids":["https://openalex.org/I4210094759"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5027837299","display_name":"Masahiro Fujita","orcid":"https://orcid.org/0000-0002-6516-4175"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"M. Fujita","raw_affiliation_strings":["Department of Electronic Engineering, University of Tokyo, Tokyo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, University of Tokyo, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"9","last_page":"11"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/reuse","display_name":"Reuse","score":0.6920351982116699},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6435198783874512},{"id":"https://openalex.org/keywords/abstraction","display_name":"Abstraction","score":0.6102504730224609},{"id":"https://openalex.org/keywords/time-to-market","display_name":"Time to market","score":0.5114878416061401},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.5108120441436768},{"id":"https://openalex.org/keywords/software-engineering","display_name":"Software engineering","score":0.48529189825057983},{"id":"https://openalex.org/keywords/current","display_name":"Current (fluid)","score":0.45848649740219116},{"id":"https://openalex.org/keywords/electronic-system-level-design-and-verification","display_name":"Electronic system-level design and verification","score":0.45236510038375854},{"id":"https://openalex.org/keywords/systems-engineering","display_name":"Systems engineering","score":0.42775759100914},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.42016342282295227},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.4184921979904175},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.34384891390800476},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20282286405563354},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.15015482902526855},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.12810546159744263},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.08405604958534241}],"concepts":[{"id":"https://openalex.org/C206588197","wikidata":"https://www.wikidata.org/wiki/Q846574","display_name":"Reuse","level":2,"score":0.6920351982116699},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6435198783874512},{"id":"https://openalex.org/C124304363","wikidata":"https://www.wikidata.org/wiki/Q673661","display_name":"Abstraction","level":2,"score":0.6102504730224609},{"id":"https://openalex.org/C2779229675","wikidata":"https://www.wikidata.org/wiki/Q445235","display_name":"Time to market","level":2,"score":0.5114878416061401},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.5108120441436768},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.48529189825057983},{"id":"https://openalex.org/C148043351","wikidata":"https://www.wikidata.org/wiki/Q4456944","display_name":"Current (fluid)","level":2,"score":0.45848649740219116},{"id":"https://openalex.org/C77495112","wikidata":"https://www.wikidata.org/wiki/Q5358436","display_name":"Electronic system-level design and verification","level":2,"score":0.45236510038375854},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.42775759100914},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.42016342282295227},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4184921979904175},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.34384891390800476},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20282286405563354},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.15015482902526855},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.12810546159744263},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.08405604958534241},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C548081761","wikidata":"https://www.wikidata.org/wiki/Q180388","display_name":"Waste management","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icvd.2004.1260892","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icvd.2004.1260892","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"17th International Conference on VLSI Design. Proceedings.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.44999998807907104}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W4253195573","https://openalex.org/W2020934033","https://openalex.org/W63276784","https://openalex.org/W2016926482","https://openalex.org/W2059530328","https://openalex.org/W3011978806","https://openalex.org/W2129671278","https://openalex.org/W4230718388","https://openalex.org/W1585773602","https://openalex.org/W1583557603"],"abstract_inverted_index":{"This":[0],"paper":[1],"describes":[2],"about":[3],"the":[4,20,29],"increasing":[5],"complexity":[6],"of":[7,31,34],"VLSI":[8],"design,":[9],"time":[10],"to":[11,18],"market":[12],"pressures.":[13],"The":[14],"two":[15],"major":[16],"paradigms":[17],"address":[19],"difficulties":[21],"currently":[22],"being":[23],"faced":[24],"by":[25],"industry":[26],"are:":[27],"(1)":[28],"use":[30],"higher":[32],"levels":[33],"design":[35,42,51],"abstraction":[36],"and":[37,40,47,53],"(2)":[38],"efficient":[39],"seamless":[41],"reuse.":[43],"Current":[44],"industrial":[45],"practices":[46],"academic":[48],"research":[49],"in":[50],"verification":[52],"validation":[54],"are":[55],"also":[56],"discussed.":[57]},"counts_by_year":[],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
