{"id":"https://openalex.org/W1742027870","doi":"https://doi.org/10.1109/icvd.2004.1260891","title":"Physical design trends and layout-based fault modeling","display_name":"Physical design trends and layout-based fault modeling","publication_year":2004,"publication_date":"2004-06-21","ids":{"openalex":"https://openalex.org/W1742027870","doi":"https://doi.org/10.1109/icvd.2004.1260891","mag":"1742027870"},"language":"en","primary_location":{"id":"doi:10.1109/icvd.2004.1260891","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icvd.2004.1260891","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"17th International Conference on VLSI Design. Proceedings.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5021904459","display_name":"Susmita Sur\u2010Kolay","orcid":"https://orcid.org/0000-0002-2052-3779"},"institutions":[{"id":"https://openalex.org/I6498739","display_name":"Indian Statistical Institute","ror":"https://ror.org/00q2w1j53","country_code":"IN","type":"education","lineage":["https://openalex.org/I6498739"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"S. Sur-Kolay","raw_affiliation_strings":["Indian Statistical Institute, Kolkata, India","Indian Stat. Inst., Kolkata, India"],"affiliations":[{"raw_affiliation_string":"Indian Statistical Institute, Kolkata, India","institution_ids":["https://openalex.org/I6498739"]},{"raw_affiliation_string":"Indian Stat. Inst., Kolkata, India","institution_ids":["https://openalex.org/I6498739"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5056511273","display_name":"Partha Dasgupta","orcid":null},"institutions":[{"id":"https://openalex.org/I71495548","display_name":"Indian Institute of Management Calcutta","ror":"https://ror.org/02zhewk16","country_code":"IN","type":"education","lineage":["https://openalex.org/I71495548"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"P. Dasgupta","raw_affiliation_strings":["Indian Institute of Management, Calcutta, India","Indian Institute of Management-Calcutta#TAB#"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Management, Calcutta, India","institution_ids":["https://openalex.org/I71495548"]},{"raw_affiliation_string":"Indian Institute of Management-Calcutta#TAB#","institution_ids":["https://openalex.org/I71495548"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052870102","display_name":"Bhaswar B. Bhattacharya","orcid":"https://orcid.org/0000-0002-2528-843X"},"institutions":[{"id":"https://openalex.org/I6498739","display_name":"Indian Statistical Institute","ror":"https://ror.org/00q2w1j53","country_code":"IN","type":"education","lineage":["https://openalex.org/I6498739"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"B.B. Bhattacharya","raw_affiliation_strings":["Indian Statistical Institute, Kolkata, India","Indian Statistical institute, Kolkata#TAB#"],"affiliations":[{"raw_affiliation_string":"Indian Statistical Institute, Kolkata, India","institution_ids":["https://openalex.org/I6498739"]},{"raw_affiliation_string":"Indian Statistical institute, Kolkata#TAB#","institution_ids":["https://openalex.org/I6498739"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5016040904","display_name":"S.T. Zachariah","orcid":null},"institutions":[{"id":"https://openalex.org/I4210146682","display_name":"Intel (India)","ror":"https://ror.org/04f2n1245","country_code":"IN","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210146682"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"S.T. Zachariah","raw_affiliation_strings":["Intel India Development Centre, Bangalore, India","Intel India Development Centre, Bangalore"],"affiliations":[{"raw_affiliation_string":"Intel India Development Centre, Bangalore, India","institution_ids":["https://openalex.org/I4210146682"]},{"raw_affiliation_string":"Intel India Development Centre, Bangalore","institution_ids":["https://openalex.org/I4210146682"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5021904459"],"corresponding_institution_ids":["https://openalex.org/I6498739"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.08912958,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"6","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.8362044095993042},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.7740307450294495},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.6388161182403564},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.613885760307312},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.5922189354896545},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.5780941843986511},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.559293806552887},{"id":"https://openalex.org/keywords/fault","display_name":"Fault (geology)","score":0.5359761118888855},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.5190954208374023},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.49732187390327454},{"id":"https://openalex.org/keywords/fault-coverage","display_name":"Fault coverage","score":0.4675060212612152},{"id":"https://openalex.org/keywords/predictability","display_name":"Predictability","score":0.43027591705322266},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.27756595611572266},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2614303529262543},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.26014119386672974},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.22434058785438538},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.09894317388534546},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.0842328667640686}],"concepts":[{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.8362044095993042},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.7740307450294495},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.6388161182403564},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.613885760307312},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.5922189354896545},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.5780941843986511},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.559293806552887},{"id":"https://openalex.org/C175551986","wikidata":"https://www.wikidata.org/wiki/Q47089","display_name":"Fault (geology)","level":2,"score":0.5359761118888855},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.5190954208374023},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.49732187390327454},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.4675060212612152},{"id":"https://openalex.org/C197640229","wikidata":"https://www.wikidata.org/wiki/Q2534066","display_name":"Predictability","level":2,"score":0.43027591705322266},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.27756595611572266},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2614303529262543},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.26014119386672974},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.22434058785438538},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.09894317388534546},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.0842328667640686},{"id":"https://openalex.org/C127313418","wikidata":"https://www.wikidata.org/wiki/Q1069","display_name":"Geology","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C165205528","wikidata":"https://www.wikidata.org/wiki/Q83371","display_name":"Seismology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icvd.2004.1260891","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icvd.2004.1260891","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"17th International Conference on VLSI Design. Proceedings.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/11","score":0.550000011920929,"display_name":"Sustainable cities and communities"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2781601456","https://openalex.org/W2115502122","https://openalex.org/W2138401961","https://openalex.org/W2353155791","https://openalex.org/W1873584906","https://openalex.org/W2223186343","https://openalex.org/W2595178692","https://openalex.org/W2798405405","https://openalex.org/W2170433636","https://openalex.org/W2102933388"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"the":[3,12,38,79,87,102,109],"concerns":[4],"and":[5,15,23,27,43,56,58,83,85],"techniques":[6],"that":[7],"are":[8,48,60,69,113],"significant":[9],"to":[10,76,107],"both":[11],"circuit":[13],"designers":[14],"developers":[16],"of":[17,78,89,104],"CAD":[18],"tools":[19],"for":[20],"physical":[21,44],"design":[22,39,45,82],"layout-based":[24],"fault":[25,96,99],"modeling":[26],"extraction.":[28],"Current":[29],"technology":[30],"trends":[31],"in":[32,41,46,53,64],"VLSI":[33],"with":[34],"their":[35],"impacts":[36],"on":[37,93],"flow":[40],"general":[42],"particular":[47],"introduced.":[49],"The":[50],"challenging":[51],"issues":[52],"partitioning,":[54],"floorplanning":[55],"placement,":[57],"routing":[59],"presented.":[61,70],"Recent":[62],"topics":[63],"deep":[65],"sub-micron":[66],"(DSM)":[67],"regime":[68],"Finally":[71],"device":[72],"scaling":[73],"has":[74],"led":[75],"blurring":[77],"boundary":[80],"between":[81],"test":[84,90,105,110],"eroded":[86],"predictability":[88],"quality":[91,111],"based":[92],"classical":[94],"stuck-at":[95],"coverage.":[97],"New":[98],"models":[100],"at":[101],"core":[103],"generation":[106],"overcome":[108],"crisis":[112],"described.":[114]},"counts_by_year":[{"year":2020,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}