{"id":"https://openalex.org/W2118946420","doi":"https://doi.org/10.1109/icvd.2003.1183188","title":"Minimum dynamic power CMOS circuit design by a reduced constraint set linear program","display_name":"Minimum dynamic power CMOS circuit design by a reduced constraint set linear program","publication_year":2003,"publication_date":"2003-08-27","ids":{"openalex":"https://openalex.org/W2118946420","doi":"https://doi.org/10.1109/icvd.2003.1183188","mag":"2118946420"},"language":"en","primary_location":{"id":"doi:10.1109/icvd.2003.1183188","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icvd.2003.1183188","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"16th International Conference on VLSI Design, 2003. Proceedings.","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5108746583","display_name":"T. Raja","orcid":null},"institutions":[{"id":"https://openalex.org/I102322142","display_name":"Rutgers, The State University of New Jersey","ror":"https://ror.org/05vt9qd57","country_code":"US","type":"education","lineage":["https://openalex.org/I102322142"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"T. Raja","raw_affiliation_strings":["Department of ECE, Rutgers University, Piscataway, NJ, USA","[Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of ECE, Rutgers University, Piscataway, NJ, USA","institution_ids":["https://openalex.org/I102322142"]},{"raw_affiliation_string":"[Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA]","institution_ids":["https://openalex.org/I102322142"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084081268","display_name":"Vishwani D. Agrawal","orcid":"https://orcid.org/0000-0002-7121-5979"},"institutions":[{"id":"https://openalex.org/I102322142","display_name":"Rutgers, The State University of New Jersey","ror":"https://ror.org/05vt9qd57","country_code":"US","type":"education","lineage":["https://openalex.org/I102322142"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"V.D. Agrawal","raw_affiliation_strings":["Department of ECE, Rutgers University, Piscataway, NJ, USA","Agere Systems"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of ECE, Rutgers University, Piscataway, NJ, USA","institution_ids":["https://openalex.org/I102322142"]},{"raw_affiliation_string":"Agere Systems","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5020404037","display_name":"M.L. Bushnell","orcid":null},"institutions":[{"id":"https://openalex.org/I102322142","display_name":"Rutgers, The State University of New Jersey","ror":"https://ror.org/05vt9qd57","country_code":"US","type":"education","lineage":["https://openalex.org/I102322142"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M.L. Bushnell","raw_affiliation_strings":["Department of ECE, Rutgers University, Piscataway, NJ, USA","Rutgers, University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of ECE, Rutgers University, Piscataway, NJ, USA","institution_ids":["https://openalex.org/I102322142"]},{"raw_affiliation_string":"Rutgers, University","institution_ids":["https://openalex.org/I102322142"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I102322142"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":27,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":"15","issue":null,"first_page":"527","last_page":"532"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.603721022605896},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5878375172615051},{"id":"https://openalex.org/keywords/constraint","display_name":"Constraint (computer-aided design)","score":0.5791870355606079},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.5601821541786194},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.5202573537826538},{"id":"https://openalex.org/keywords/delay-calculation","display_name":"Delay calculation","score":0.5141356587409973},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.4670998454093933},{"id":"https://openalex.org/keywords/dynamic-demand","display_name":"Dynamic demand","score":0.42003124952316284},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3411041498184204},{"id":"https://openalex.org/keywords/control-theory","display_name":"Control theory (sociology)","score":0.33774814009666443},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.3346191644668579},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.21533605456352234},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.159282386302948},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1551957130432129}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.603721022605896},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5878375172615051},{"id":"https://openalex.org/C2776036281","wikidata":"https://www.wikidata.org/wiki/Q48769818","display_name":"Constraint (computer-aided design)","level":2,"score":0.5791870355606079},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.5601821541786194},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.5202573537826538},{"id":"https://openalex.org/C174086752","wikidata":"https://www.wikidata.org/wiki/Q5253471","display_name":"Delay calculation","level":3,"score":0.5141356587409973},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.4670998454093933},{"id":"https://openalex.org/C45872418","wikidata":"https://www.wikidata.org/wiki/Q5318966","display_name":"Dynamic demand","level":3,"score":0.42003124952316284},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3411041498184204},{"id":"https://openalex.org/C47446073","wikidata":"https://www.wikidata.org/wiki/Q5165890","display_name":"Control theory (sociology)","level":3,"score":0.33774814009666443},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.3346191644668579},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.21533605456352234},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.159282386302948},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1551957130432129},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C2775924081","wikidata":"https://www.wikidata.org/wiki/Q55608371","display_name":"Control (management)","level":2,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/icvd.2003.1183188","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icvd.2003.1183188","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"16th International Conference on VLSI Design, 2003. Proceedings.","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.123.9336","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.123.9336","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.eng.auburn.edu/~vagrawal/TALKS/vd03_teju.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8899999856948853,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":29,"referenced_works":["https://openalex.org/W194061475","https://openalex.org/W1524395314","https://openalex.org/W1539883310","https://openalex.org/W1543643719","https://openalex.org/W1558050744","https://openalex.org/W1569550779","https://openalex.org/W1578597091","https://openalex.org/W1964166152","https://openalex.org/W1967514275","https://openalex.org/W2033724727","https://openalex.org/W2060393099","https://openalex.org/W2061480240","https://openalex.org/W2093652003","https://openalex.org/W2096424065","https://openalex.org/W2115028095","https://openalex.org/W2120666737","https://openalex.org/W2124201588","https://openalex.org/W2128306262","https://openalex.org/W2138086100","https://openalex.org/W2143093341","https://openalex.org/W2149661268","https://openalex.org/W2161828911","https://openalex.org/W2162211138","https://openalex.org/W2174953611","https://openalex.org/W2427843410","https://openalex.org/W3144286773","https://openalex.org/W4241987548","https://openalex.org/W4247494086","https://openalex.org/W6634336121"],"related_works":["https://openalex.org/W3015599398","https://openalex.org/W2034656493","https://openalex.org/W2188730438","https://openalex.org/W2157230896","https://openalex.org/W2792778858","https://openalex.org/W2572576974","https://openalex.org/W2362904186","https://openalex.org/W3008786049","https://openalex.org/W98453623","https://openalex.org/W2121192822"],"abstract_inverted_index":{"In":[0],"the":[1,4,35,38,43,48,51,62,72,78,86,94,100,112,116,151,164,177],"previous":[2,79,149],"work,":[3,150],"problem":[5],"of":[6,25,50,97,153,163],"finding":[7],"gate":[8,44],"delays":[9],"to":[10,54,71,106,118,124,142],"eliminate":[11],"glitches":[12],"has":[13],"been":[14],"solved":[15],"by":[16,93,168,182],"linear":[17,56],"programs":[18],"(LP)":[19],"requiring":[20],"an":[21,143,170],"exponentially":[22],"large":[23],"number":[24,49],"constraints.":[26,98],"By":[27],"introducing":[28],"two":[29],"additional":[30],"variables":[31],"per":[32],"gate,":[33],"namely,":[34],"fastest":[36],"and":[37,136],"slowest":[39],"arrival":[40],"times,":[41],"besides":[42],"delay,":[45],"we":[46,103],"reduce":[47],"LP":[52,89],"constraints":[53,68,75,83],"be":[55],"in":[57,148,158],"circuit":[58,65,174],"size.":[59],"For":[60,99,111],"example,":[61],"469-gate":[63],"c880":[64],"requires":[66],"3,611":[67],"as":[69,91,140],"compared":[70,141],"6.95":[73],"million":[74],"needed":[76],"with":[77,128],"method.":[80],"The":[81,161],"reduced":[82],"provably":[84],"produce":[85],"same":[87],"exact":[88],"solution":[90],"obtained":[92,181],"exponential":[95],"set":[96],"first":[101],"time,":[102],"are":[104],"able":[105],"optimize":[107],"all":[108],"ISCAS'85":[109],"benchmarks.":[110],"c7552":[113],"circuit,":[114],"when":[115],"input":[117],"output":[119],"delay":[120,130,154],"is":[121,156,166],"constrained":[122],"not":[123],"increase,":[125],"a":[126,183],"design":[127,165],"366":[129],"buffers":[131,155],"consumes":[132],"only":[133],"34%":[134],"peak":[135],"38%":[137],"average":[138],"power":[139,178],"unoptimized":[144],"design.":[145],"As":[146],"shown":[147],"use":[152],"essential":[157],"this":[159],"case.":[160],"practicality":[162],"demonstrated":[167],"implementing":[169],"optimized":[171],"4-bit":[172],"ALU":[173],"for":[175],"which":[176],"consumption":[179],"was":[180],"circuit-level":[184],"simulator.":[185]},"counts_by_year":[{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":3}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}