{"id":"https://openalex.org/W1573890454","doi":"https://doi.org/10.1109/icvd.2003.1183179","title":"Graph transformations for improved tree height reduction","display_name":"Graph transformations for improved tree height reduction","publication_year":2003,"publication_date":"2003-08-27","ids":{"openalex":"https://openalex.org/W1573890454","doi":"https://doi.org/10.1109/icvd.2003.1183179","mag":"1573890454"},"language":"en","primary_location":{"id":"doi:10.1109/icvd.2003.1183179","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icvd.2003.1183179","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"16th International Conference on VLSI Design, 2003. Proceedings.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5014208588","display_name":"G.N. Mangalam","orcid":null},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]},{"id":"https://openalex.org/I4210111610","display_name":"Cadence Design Systems (India)","ror":"https://ror.org/027qdw603","country_code":"IN","type":"company","lineage":["https://openalex.org/I4210111610","https://openalex.org/I66217453"]}],"countries":["IN","US"],"is_corresponding":true,"raw_author_name":"G.N. Mangalam","raw_affiliation_strings":["Noida Export Processing Zone, Cadence Design Systems (India) Private Limited, Noida, Uttar Pradesh, India","Cadence Design Systems, Noida, India#TAB#"],"affiliations":[{"raw_affiliation_string":"Noida Export Processing Zone, Cadence Design Systems (India) Private Limited, Noida, Uttar Pradesh, India","institution_ids":["https://openalex.org/I4210111610"]},{"raw_affiliation_string":"Cadence Design Systems, Noida, India#TAB#","institution_ids":["https://openalex.org/I66217453"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5026533006","display_name":"Sanjiv M. Narayan","orcid":"https://orcid.org/0000-0001-7552-5053"},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]},{"id":"https://openalex.org/I4210111610","display_name":"Cadence Design Systems (India)","ror":"https://ror.org/027qdw603","country_code":"IN","type":"company","lineage":["https://openalex.org/I4210111610","https://openalex.org/I66217453"]}],"countries":["IN","US"],"is_corresponding":false,"raw_author_name":"S. Narayan","raw_affiliation_strings":["Noida Export Processing Zone, Cadence Design Systems (India) Private Limited, Noida, Uttar Pradesh, India","Cadence Design Systems, Noida, India#TAB#"],"affiliations":[{"raw_affiliation_string":"Noida Export Processing Zone, Cadence Design Systems (India) Private Limited, Noida, Uttar Pradesh, India","institution_ids":["https://openalex.org/I4210111610"]},{"raw_affiliation_string":"Cadence Design Systems, Noida, India#TAB#","institution_ids":["https://openalex.org/I66217453"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5007730443","display_name":"P. van Besouw","orcid":null},"institutions":[{"id":"https://openalex.org/I4210111610","display_name":"Cadence Design Systems (India)","ror":"https://ror.org/027qdw603","country_code":"IN","type":"company","lineage":["https://openalex.org/I4210111610","https://openalex.org/I66217453"]},{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["IN","US"],"is_corresponding":false,"raw_author_name":"P. van Besouw","raw_affiliation_strings":["Noida Export Processing Zone, Cadence Design Systems (India) Private Limited, Noida, Uttar Pradesh, India","Cadence Design Systems, Noida, India#TAB#"],"affiliations":[{"raw_affiliation_string":"Noida Export Processing Zone, Cadence Design Systems (India) Private Limited, Noida, Uttar Pradesh, India","institution_ids":["https://openalex.org/I4210111610"]},{"raw_affiliation_string":"Cadence Design Systems, Noida, India#TAB#","institution_ids":["https://openalex.org/I66217453"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5020113250","display_name":"L.N. Avra","orcid":null},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]},{"id":"https://openalex.org/I4210111610","display_name":"Cadence Design Systems (India)","ror":"https://ror.org/027qdw603","country_code":"IN","type":"company","lineage":["https://openalex.org/I4210111610","https://openalex.org/I66217453"]}],"countries":["IN","US"],"is_corresponding":false,"raw_author_name":"L.N. Avra","raw_affiliation_strings":["Noida Export Processing Zone, Cadence Design Systems (India) Private Limited, Noida, Uttar Pradesh, India","Cadence Design Systems, Noida, India#TAB#"],"affiliations":[{"raw_affiliation_string":"Noida Export Processing Zone, Cadence Design Systems (India) Private Limited, Noida, Uttar Pradesh, India","institution_ids":["https://openalex.org/I4210111610"]},{"raw_affiliation_string":"Cadence Design Systems, Noida, India#TAB#","institution_ids":["https://openalex.org/I66217453"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041431658","display_name":"Aditya P. Mathur","orcid":"https://orcid.org/0000-0002-9356-6286"},"institutions":[{"id":"https://openalex.org/I4210111610","display_name":"Cadence Design Systems (India)","ror":"https://ror.org/027qdw603","country_code":"IN","type":"company","lineage":["https://openalex.org/I4210111610","https://openalex.org/I66217453"]},{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["IN","US"],"is_corresponding":false,"raw_author_name":"A. Mathur","raw_affiliation_strings":["Noida Export Processing Zone, Cadence Design Systems (India) Private Limited, Noida, Uttar Pradesh, India","Cadence Design Systems, Noida, India#TAB#"],"affiliations":[{"raw_affiliation_string":"Noida Export Processing Zone, Cadence Design Systems (India) Private Limited, Noida, Uttar Pradesh, India","institution_ids":["https://openalex.org/I4210111610"]},{"raw_affiliation_string":"Cadence Design Systems, Noida, India#TAB#","institution_ids":["https://openalex.org/I66217453"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5113497566","display_name":"Sanjeev Saluja","orcid":null},"institutions":[{"id":"https://openalex.org/I4210111610","display_name":"Cadence Design Systems (India)","ror":"https://ror.org/027qdw603","country_code":"IN","type":"company","lineage":["https://openalex.org/I4210111610","https://openalex.org/I66217453"]},{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["IN","US"],"is_corresponding":false,"raw_author_name":"S. Saluja","raw_affiliation_strings":["Noida Export Processing Zone, Cadence Design Systems (India) Private Limited, Noida, Uttar Pradesh, India","Cadence Design Systems, Noida, India#TAB#"],"affiliations":[{"raw_affiliation_string":"Noida Export Processing Zone, Cadence Design Systems (India) Private Limited, Noida, Uttar Pradesh, India","institution_ids":["https://openalex.org/I4210111610"]},{"raw_affiliation_string":"Cadence Design Systems, Noida, India#TAB#","institution_ids":["https://openalex.org/I66217453"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5014208588"],"corresponding_institution_ids":["https://openalex.org/I4210111610","https://openalex.org/I66217453"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.05815879,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"474","last_page":"479"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/datapath","display_name":"Datapath","score":0.6170676350593567},{"id":"https://openalex.org/keywords/graph","display_name":"Graph","score":0.6079734563827515},{"id":"https://openalex.org/keywords/graph-reduction","display_name":"Graph reduction","score":0.5481111407279968},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.5146156549453735},{"id":"https://openalex.org/keywords/tree","display_name":"Tree (set theory)","score":0.44916635751724243},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.4452993869781494},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.4313446283340454},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.41797709465026855},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3857060968875885},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.3229356110095978},{"id":"https://openalex.org/keywords/discrete-mathematics","display_name":"Discrete mathematics","score":0.2718868851661682},{"id":"https://openalex.org/keywords/combinatorics","display_name":"Combinatorics","score":0.24373948574066162},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.21149474382400513},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.16459697484970093}],"concepts":[{"id":"https://openalex.org/C2781198647","wikidata":"https://www.wikidata.org/wiki/Q1633673","display_name":"Datapath","level":2,"score":0.6170676350593567},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.6079734563827515},{"id":"https://openalex.org/C97042676","wikidata":"https://www.wikidata.org/wiki/Q5597097","display_name":"Graph reduction","level":3,"score":0.5481111407279968},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.5146156549453735},{"id":"https://openalex.org/C113174947","wikidata":"https://www.wikidata.org/wiki/Q2859736","display_name":"Tree (set theory)","level":2,"score":0.44916635751724243},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.4452993869781494},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.4313446283340454},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.41797709465026855},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3857060968875885},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.3229356110095978},{"id":"https://openalex.org/C118615104","wikidata":"https://www.wikidata.org/wiki/Q121416","display_name":"Discrete mathematics","level":1,"score":0.2718868851661682},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.24373948574066162},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.21149474382400513},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.16459697484970093},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C42383842","wikidata":"https://www.wikidata.org/wiki/Q193076","display_name":"Functional programming","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icvd.2003.1183179","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icvd.2003.1183179","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"16th International Conference on VLSI Design, 2003. Proceedings.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1491178396","https://openalex.org/W2116468471","https://openalex.org/W2151867075","https://openalex.org/W2535493751","https://openalex.org/W6728672537"],"related_works":["https://openalex.org/W2109699519","https://openalex.org/W2006568360","https://openalex.org/W102726818","https://openalex.org/W4233616027","https://openalex.org/W2059591361","https://openalex.org/W970262775","https://openalex.org/W4244724753","https://openalex.org/W1972081536","https://openalex.org/W2535673728","https://openalex.org/W1831618318"],"abstract_inverted_index":{"Tree":[0],"height":[1,28,39,131],"reduction":[2,40,132],"helps":[3],"in":[4,12,20,49,55,69,96,107,137],"minimizing":[5],"the":[6,23,70,93,97],"critical":[7,138],"path":[8,139],"delay":[9,140],"and":[10,32,99,141],"area":[11],"datapath":[13],"rich":[14],"designs":[15,123],"during":[16],"synthesis.":[17],"We":[18],"introduce":[19],"this":[21],"paper,":[22],"necessary":[24],"conditions":[25],"to":[26,92,114],"identify":[27],"reducible":[29],"arithmetic":[30,65],"expressions":[31],"three":[33],"graph":[34,77,105,126],"transformations":[35,127],"that":[36,53,62],"make":[37],"tree":[38,130],"more":[41],"efficient:":[42],"(a)":[43],"bit-width":[44],"matching":[45],"-":[46,75,103],"a":[47,76,104,116],"technique":[48],"which":[50,80,108],"input":[51],"signals":[52],"match":[54],"their":[56],"bit-widths":[57],"are":[58,67,88,111],"grouped":[59,112],"together":[60,113],"so":[61],"smaller":[63],"width":[64],"nodes":[66,95],"created":[68],"graph;":[71,98],"(b)":[72],"carry/borrow":[73,91],"optimization":[74],"transformation":[78,106],"by":[79],"an":[81],"optimum":[82],"number":[83],"of":[84,118],"single":[85],"bit":[86],"inputs":[87,110],"distributed":[89],"as":[90],"add/subtract":[94],"(c)":[100],"constant":[101,109],"grouping":[102],"form":[115],"sub-tree":[117],"constants.":[119],"Experiments":[120],"on":[121],"industrial":[122],"with":[124,129],"these":[125],"coupled":[128],"have":[133],"shown":[134],"significant":[135],"improvement":[136],"area.":[142]},"counts_by_year":[{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
