{"id":"https://openalex.org/W2146142440","doi":"https://doi.org/10.1109/icvd.2003.1183146","title":"High level synthesis from Sim-nML processor models","display_name":"High level synthesis from Sim-nML processor models","publication_year":2003,"publication_date":"2003-08-27","ids":{"openalex":"https://openalex.org/W2146142440","doi":"https://doi.org/10.1109/icvd.2003.1183146","mag":"2146142440"},"language":"en","primary_location":{"id":"doi:10.1109/icvd.2003.1183146","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icvd.2003.1183146","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"16th International Conference on VLSI Design, 2003. Proceedings.","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5056774275","display_name":"Sriparna Basu","orcid":"https://orcid.org/0000-0001-7924-8153"},"institutions":[{"id":"https://openalex.org/I3132308339","display_name":"Government Dental College & Research Institute","ror":"https://ror.org/028qd3f30","country_code":"IN","type":"education","lineage":["https://openalex.org/I286135121","https://openalex.org/I3132308339"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"S. Basu","raw_affiliation_strings":["GDA Technologies Limited, Bangalore, India","GDA Technol. Ltd., Bangalore, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"GDA Technologies Limited, Bangalore, India","institution_ids":[]},{"raw_affiliation_string":"GDA Technol. Ltd., Bangalore, India","institution_ids":["https://openalex.org/I3132308339"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5059289976","display_name":"Rajat Moona","orcid":null},"institutions":[{"id":"https://openalex.org/I94234084","display_name":"Indian Institute of Technology Kanpur","ror":"https://ror.org/05pjsgx75","country_code":"IN","type":"education","lineage":["https://openalex.org/I94234084"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"R. Moona","raw_affiliation_strings":["Department of CSE, IIT, Kanpur, India","Indian Institute of Technology Kanpur \u2028"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of CSE, IIT, Kanpur, India","institution_ids":["https://openalex.org/I94234084"]},{"raw_affiliation_string":"Indian Institute of Technology Kanpur \u2028","institution_ids":["https://openalex.org/I94234084"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.4662,"has_fulltext":false,"cited_by_count":20,"citation_normalized_percentile":{"value":0.616261,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"255","last_page":"260"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.8348703384399414},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7768232226371765},{"id":"https://openalex.org/keywords/abstraction","display_name":"Abstraction","score":0.7599794864654541},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.6409673094749451},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.6078045964241028},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5029084086418152},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.471193790435791},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.4559231102466583},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3622255325317383},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.28957509994506836},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.22122660279273987}],"concepts":[{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.8348703384399414},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7768232226371765},{"id":"https://openalex.org/C124304363","wikidata":"https://www.wikidata.org/wiki/Q673661","display_name":"Abstraction","level":2,"score":0.7599794864654541},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.6409673094749451},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.6078045964241028},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5029084086418152},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.471193790435791},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.4559231102466583},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3622255325317383},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.28957509994506836},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.22122660279273987},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/icvd.2003.1183146","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icvd.2003.1183146","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"16th International Conference on VLSI Design, 2003. Proceedings.","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.108.3319","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.108.3319","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.cse.iitk.ac.in/~moona/papers/basu.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.90.4760","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.90.4760","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.cecs.uci.edu/~papers/vlsid03/DATA/10_03.PDF","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":25,"referenced_works":["https://openalex.org/W53002652","https://openalex.org/W1567363020","https://openalex.org/W1683919907","https://openalex.org/W1749533968","https://openalex.org/W1957956207","https://openalex.org/W2010074783","https://openalex.org/W2014714034","https://openalex.org/W2024347417","https://openalex.org/W2063747323","https://openalex.org/W2118229154","https://openalex.org/W2118387410","https://openalex.org/W2145946269","https://openalex.org/W2162479472","https://openalex.org/W2166908749","https://openalex.org/W2434681313","https://openalex.org/W2493328864","https://openalex.org/W2493822152","https://openalex.org/W2542693654","https://openalex.org/W4231517789","https://openalex.org/W4232714327","https://openalex.org/W4245411879","https://openalex.org/W4285719527","https://openalex.org/W6637601185","https://openalex.org/W6666553449","https://openalex.org/W6718279959"],"related_works":["https://openalex.org/W2107240870","https://openalex.org/W2136295006","https://openalex.org/W1761969858","https://openalex.org/W2165480138","https://openalex.org/W2005854230","https://openalex.org/W2107517480","https://openalex.org/W2168113051","https://openalex.org/W2916312349","https://openalex.org/W2132512458","https://openalex.org/W2077870657"],"abstract_inverted_index":{"The":[0,16],"design":[1],"of":[2,11,13,59,72],"modern":[3],"complex":[4],"embedded":[5],"systems":[6],"require":[7],"a":[8,19,48,73],"high":[9,53],"level":[10,54],"abstraction":[12],"the":[14,76],"design.":[15],"Sim-nML":[17,40,70,98],"is":[18,82],"specification":[20],"language":[21],"to":[22,75],"model":[23,80,95],"processors":[24,60],"for":[25,84],"such":[26],"designs.":[27],"Several":[28],"software":[29],"generation":[30],"tools":[31],"have":[32],"been":[33],"developed":[34],"that":[35,51,81],"take":[36],"ISA":[37,63],"specifications":[38,64,71],"in":[39,65],"as":[41],"input.":[42],"In":[43],"this":[44],"paper":[45],"we":[46],"present":[47],"tool":[49],"Sim-HS":[50,68,89],"implements":[52],"behavioral":[55,78],"and":[56],"structural":[57,91],"synthesis":[58],"from":[61,96],"their":[62],"Sim-nML.":[66],"Behavioral":[67],"transforms":[69],"processor":[74,94],"corresponding":[77],"Verilog":[79,93],"suitable":[83],"fast":[85],"functional":[86],"simulation.":[87],"Structural":[88],"generates":[90],"synthesizable":[92],"its":[97],"specifications.":[99]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":4},{"year":2015,"cited_by_count":2},{"year":2012,"cited_by_count":3}],"updated_date":"2026-08-26T07:47:46.906454","created_date":"2025-10-10T00:00:00"}
