{"id":"https://openalex.org/W2168081446","doi":"https://doi.org/10.1109/icvd.2003.1183144","title":"Formal verification using bounded model checking: SAT versus sequential ATPG engines","display_name":"Formal verification using bounded model checking: SAT versus sequential ATPG engines","publication_year":2003,"publication_date":"2003-08-27","ids":{"openalex":"https://openalex.org/W2168081446","doi":"https://doi.org/10.1109/icvd.2003.1183144","mag":"2168081446"},"language":"en","primary_location":{"id":"doi:10.1109/icvd.2003.1183144","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icvd.2003.1183144","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"16th International Conference on VLSI Design, 2003. Proceedings.","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5021334492","display_name":"D.G. Saab","orcid":null},"institutions":[{"id":"https://openalex.org/I58956616","display_name":"Case Western Reserve University","ror":"https://ror.org/051fd9666","country_code":"US","type":"education","lineage":["https://openalex.org/I58956616"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"D.G. Saab","raw_affiliation_strings":["Department of Electrical Engineering and Computer Science, Case Western Reserve University, Cleveland, OH, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering and Computer Science, Case Western Reserve University, Cleveland, OH, USA","institution_ids":["https://openalex.org/I58956616"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5068070739","display_name":"Jacob A. Abraham","orcid":"https://orcid.org/0000-0002-5336-5631"},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J.A. Abraham","raw_affiliation_strings":["Computer Engineering Research Center, University of Technology, Austin, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Engineering Research Center, University of Technology, Austin, TX, USA","institution_ids":["https://openalex.org/I86519309"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5112274608","display_name":"V.M. Vedula","orcid":null},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"V.M. Vedula","raw_affiliation_strings":["Computer Engineering Research Center, University of Technology, Austin, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Engineering Research Center, University of Technology, Austin, TX, USA","institution_ids":["https://openalex.org/I86519309"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":16,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"243","last_page":"248"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10743","display_name":"Software Testing and Debugging Techniques","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/1712","display_name":"Software"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.8543139696121216},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7199667692184448},{"id":"https://openalex.org/keywords/correctness","display_name":"Correctness","score":0.7122952938079834},{"id":"https://openalex.org/keywords/satisfiability","display_name":"Satisfiability","score":0.6020942330360413},{"id":"https://openalex.org/keywords/boolean-satisfiability-problem","display_name":"Boolean satisfiability problem","score":0.5414727926254272},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.5249906778335571},{"id":"https://openalex.org/keywords/model-checking","display_name":"Model checking","score":0.5096423625946045},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.46746519207954407},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.3520936667919159},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.3297225534915924},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.09288513660430908}],"concepts":[{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.8543139696121216},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7199667692184448},{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.7122952938079834},{"id":"https://openalex.org/C168773769","wikidata":"https://www.wikidata.org/wiki/Q1350299","display_name":"Satisfiability","level":2,"score":0.6020942330360413},{"id":"https://openalex.org/C6943359","wikidata":"https://www.wikidata.org/wiki/Q875276","display_name":"Boolean satisfiability problem","level":2,"score":0.5414727926254272},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.5249906778335571},{"id":"https://openalex.org/C110251889","wikidata":"https://www.wikidata.org/wiki/Q1569697","display_name":"Model checking","level":2,"score":0.5096423625946045},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.46746519207954407},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.3520936667919159},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.3297225534915924},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.09288513660430908},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icvd.2003.1183144","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icvd.2003.1183144","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"16th International Conference on VLSI Design, 2003. Proceedings.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.6299999952316284}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":31,"referenced_works":["https://openalex.org/W1490969264","https://openalex.org/W1493721853","https://openalex.org/W1503170978","https://openalex.org/W1540180960","https://openalex.org/W1555280138","https://openalex.org/W1573354578","https://openalex.org/W1712855703","https://openalex.org/W1787074469","https://openalex.org/W1838320025","https://openalex.org/W1903629970","https://openalex.org/W1970603830","https://openalex.org/W2011039300","https://openalex.org/W2048051309","https://openalex.org/W2062897452","https://openalex.org/W2071868930","https://openalex.org/W2117189826","https://openalex.org/W2132334337","https://openalex.org/W2134693502","https://openalex.org/W2134825351","https://openalex.org/W2142785340","https://openalex.org/W2146662253","https://openalex.org/W2170826919","https://openalex.org/W2180713429","https://openalex.org/W4231640108","https://openalex.org/W4252315883","https://openalex.org/W4285719527","https://openalex.org/W4300021588","https://openalex.org/W6632304951","https://openalex.org/W6638020115","https://openalex.org/W6662401534","https://openalex.org/W6684722583"],"related_works":["https://openalex.org/W2127167802","https://openalex.org/W2360180534","https://openalex.org/W2109674123","https://openalex.org/W3176904788","https://openalex.org/W4256313551","https://openalex.org/W2165929878","https://openalex.org/W2146907344","https://openalex.org/W21597398","https://openalex.org/W2604391196","https://openalex.org/W2091617677"],"abstract_inverted_index":{"Industry":[0],"is":[1],"beginning":[2],"to":[3,57],"use":[4],"Satisfiability":[5],"(SAT)":[6],"solvers":[7,26],"extensively":[8],"for":[9,35,71],"formally":[10],"verifying":[11],"the":[12,22,42,51],"correctness":[13],"of":[14,24,50],"digital":[15],"designs.":[16,73],"In":[17],"this":[18],"paper":[19],"we":[20],"compare":[21],"performance":[23],"SAT":[25,66],"with":[27],"sequential":[28],"Automatic":[29],"Test":[30],"Pattern":[31],"Generation":[32],"(ATPG)":[33],"techniques":[34,61],"property":[36],"verification.":[37],"Our":[38],"experimental":[39],"results":[40],"on":[41],"ISCAS":[43],"benchmarks":[44],"as":[45,47],"well":[46],"a":[48],"model":[49],"8085":[52],"microprocessor":[53],"show":[54],"that,":[55],"contrary":[56],"popular":[58],"belief,":[59],"ATPG":[60],"perform":[62],"much":[63],"better":[64],"than":[65],"based":[67],"verification":[68],"techniques,":[69],"especially":[70],"large":[72]},"counts_by_year":[{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}