{"id":"https://openalex.org/W1605997825","doi":"https://doi.org/10.1109/icvd.2003.1183107","title":"Specification and design of multi-million gate SOCs","display_name":"Specification and design of multi-million gate SOCs","publication_year":2003,"publication_date":"2003-08-27","ids":{"openalex":"https://openalex.org/W1605997825","doi":"https://doi.org/10.1109/icvd.2003.1183107","mag":"1605997825"},"language":"en","primary_location":{"id":"doi:10.1109/icvd.2003.1183107","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icvd.2003.1183107","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"16th International Conference on VLSI Design, 2003. Proceedings.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"R. Chandra","orcid":null},"institutions":[{"id":"https://openalex.org/I4210106035","display_name":"STMicroelectronics (United States)","ror":"https://ror.org/01f8c3y78","country_code":"US","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210106035"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"R. Chandra","raw_affiliation_strings":["STMicroelectronics, Inc., USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"STMicroelectronics, Inc., USA","institution_ids":["https://openalex.org/I4210106035"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108423074","display_name":"J\u00f6rg Henkel","orcid":null},"institutions":[{"id":"https://openalex.org/I4210107353","display_name":"NEC (United States)","ror":"https://ror.org/01v791m31","country_code":"US","type":"company","lineage":["https://openalex.org/I118347220","https://openalex.org/I4210107353"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J. Henkel","raw_affiliation_strings":["NEC Limited, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"NEC Limited, USA","institution_ids":["https://openalex.org/I4210107353"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5027215692","display_name":"Preeti Ranjan Panda","orcid":"https://orcid.org/0000-0002-2508-7531"},"institutions":[{"id":"https://openalex.org/I68891433","display_name":"Indian Institute of Technology Delhi","ror":"https://ror.org/049tgcd06","country_code":"IN","type":"education","lineage":["https://openalex.org/I68891433"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"P.R. Panda","raw_affiliation_strings":["Indian Institute of Technology, New Delhi, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology, New Delhi, India","institution_ids":["https://openalex.org/I68891433"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5030042327","display_name":"Sri Parameswaran","orcid":"https://orcid.org/0000-0003-0435-9080"},"institutions":[{"id":"https://openalex.org/I31746571","display_name":"UNSW Sydney","ror":"https://ror.org/03r8z3t63","country_code":"AU","type":"education","lineage":["https://openalex.org/I31746571"]}],"countries":["AU"],"is_corresponding":false,"raw_author_name":"S. Parameswaran","raw_affiliation_strings":["University of New South Wales, Australia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of New South Wales, Australia","institution_ids":["https://openalex.org/I31746571"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5112561033","display_name":"Loganath Ramachandran","orcid":null},"institutions":[{"id":"https://openalex.org/I4210088951","display_name":"Synopsys (United States)","ror":"https://ror.org/013by2m91","country_code":"US","type":"company","lineage":["https://openalex.org/I4210088951"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"L. Ramachandran","raw_affiliation_strings":["Synopsys, Inc., USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Synopsys, Inc., USA","institution_ids":["https://openalex.org/I4210088951"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.07092066,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"18","last_page":"19"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9973000288009644,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7185860872268677},{"id":"https://openalex.org/keywords/electronic-system-level-design-and-verification","display_name":"Electronic system-level design and verification","score":0.6048922538757324},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.5974636077880859},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.580592155456543},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5786746740341187},{"id":"https://openalex.org/keywords/functional-verification","display_name":"Functional verification","score":0.5501627326011658},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.5284637808799744},{"id":"https://openalex.org/keywords/closing","display_name":"Closing (real estate)","score":0.4968102276325226},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.4217076301574707},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.41966167092323303},{"id":"https://openalex.org/keywords/intelligent-verification","display_name":"Intelligent verification","score":0.41291525959968567},{"id":"https://openalex.org/keywords/software-system","display_name":"Software system","score":0.18500638008117676},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.14420214295387268},{"id":"https://openalex.org/keywords/software-construction","display_name":"Software construction","score":0.14415764808654785},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.10659080743789673}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7185860872268677},{"id":"https://openalex.org/C77495112","wikidata":"https://www.wikidata.org/wiki/Q5358436","display_name":"Electronic system-level design and verification","level":2,"score":0.6048922538757324},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5974636077880859},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.580592155456543},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5786746740341187},{"id":"https://openalex.org/C62460635","wikidata":"https://www.wikidata.org/wiki/Q5508853","display_name":"Functional verification","level":3,"score":0.5501627326011658},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.5284637808799744},{"id":"https://openalex.org/C2778775528","wikidata":"https://www.wikidata.org/wiki/Q5135432","display_name":"Closing (real estate)","level":2,"score":0.4968102276325226},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.4217076301574707},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.41966167092323303},{"id":"https://openalex.org/C3406870","wikidata":"https://www.wikidata.org/wiki/Q6044160","display_name":"Intelligent verification","level":5,"score":0.41291525959968567},{"id":"https://openalex.org/C149091818","wikidata":"https://www.wikidata.org/wiki/Q2429814","display_name":"Software system","level":3,"score":0.18500638008117676},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.14420214295387268},{"id":"https://openalex.org/C186846655","wikidata":"https://www.wikidata.org/wiki/Q3398377","display_name":"Software construction","level":4,"score":0.14415764808654785},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.10659080743789673},{"id":"https://openalex.org/C17744445","wikidata":"https://www.wikidata.org/wiki/Q36442","display_name":"Political science","level":0,"score":0.0},{"id":"https://openalex.org/C199539241","wikidata":"https://www.wikidata.org/wiki/Q7748","display_name":"Law","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icvd.2003.1183107","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icvd.2003.1183107","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"16th International Conference on VLSI Design, 2003. Proceedings.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W3120172095","https://openalex.org/W2153955347","https://openalex.org/W2106507440","https://openalex.org/W2135756607","https://openalex.org/W4255789569","https://openalex.org/W2130564948","https://openalex.org/W2535719568","https://openalex.org/W2379784933","https://openalex.org/W4389429005","https://openalex.org/W1995589254"],"abstract_inverted_index":{"Summary":[0],"form":[1],"only":[2],"given.":[3],"Recent":[4],"advances":[5],"in":[6,74],"semiconductor":[7],"technology":[8],"have":[9],"made":[10],"it":[11],"possible":[12],"to":[13,63],"integrate":[14],"multi":[15],"million":[16],"transistors":[17],"on":[18,46],"a":[19],"single":[20],"chip;":[21],"design":[22,76],"and":[23,38,56,59,77],"verification":[24,39,78],"teams":[25],"face":[26],"several":[27],"challenges":[28,35],"managing":[29],"the":[30,41,47,54,61,66,72],"complexity.":[31],"Some":[32],"of":[33,53,65],"these":[34],"include,":[36],"specification":[37],"at":[40],"functional":[42],"level,":[43],"closing":[44],"early":[45],"system":[48],"level":[49],"architecture,":[50],"extensive":[51],"simulations":[52],"hardware":[55],"software":[57],"components":[58],"finalizing":[60],"path":[62],"implementation":[64],"entire":[67],"SOC.":[68],"This":[69],"tutorial":[70],"covers":[71],"state-of-the-art":[73],"specification,":[75],"techniques.":[79]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}