{"id":"https://openalex.org/W3127845477","doi":"https://doi.org/10.1109/icta50426.2020.9332120","title":"A 0.7-V Clock-gating Cell with Power Gating Technology and 1.56-pA Sleep Power","display_name":"A 0.7-V Clock-gating Cell with Power Gating Technology and 1.56-pA Sleep Power","publication_year":2020,"publication_date":"2020-11-23","ids":{"openalex":"https://openalex.org/W3127845477","doi":"https://doi.org/10.1109/icta50426.2020.9332120","mag":"3127845477"},"language":"en","primary_location":{"id":"doi:10.1109/icta50426.2020.9332120","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icta50426.2020.9332120","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5022116222","display_name":"Songyao Tan","orcid":null},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Songyao Tan","raw_affiliation_strings":["Tsinghua University, Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5011774751","display_name":"Yue Yin","orcid":"https://orcid.org/0000-0001-5651-3233"},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yue Yin","raw_affiliation_strings":["Tsinghua University, Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063888012","display_name":"Hanjun Jiang","orcid":"https://orcid.org/0000-0003-4911-0748"},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Hanjun Jiang","raw_affiliation_strings":["Tsinghua University, Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100356864","display_name":"Zhihua Wang","orcid":"https://orcid.org/0000-0001-6567-0759"},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhihua Wang","raw_affiliation_strings":["Research Institute of Tsinghua University in Shenzhen, Guangdong, China","Tsinghua University, Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Research Institute of Tsinghua University in Shenzhen, Guangdong, China","institution_ids":["https://openalex.org/I99065089"]},{"raw_affiliation_string":"Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I99065089"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.15874289,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"77","last_page":"78"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.9185401201248169},{"id":"https://openalex.org/keywords/power-gating","display_name":"Power gating","score":0.8779186010360718},{"id":"https://openalex.org/keywords/low-power-electronics","display_name":"Low-power electronics","score":0.5980286598205566},{"id":"https://openalex.org/keywords/dynamic-demand","display_name":"Dynamic demand","score":0.5618466734886169},{"id":"https://openalex.org/keywords/gating","display_name":"Gating","score":0.5514720678329468},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.5403748750686646},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.49822115898132324},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4819228947162628},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4363314211368561},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.43013519048690796},{"id":"https://openalex.org/keywords/sleep-mode","display_name":"Sleep mode","score":0.4177713096141815},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.39774033427238464},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3969497084617615},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.3698056936264038},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2815205752849579},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.21942946314811707},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.1460099220275879},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.1328868269920349}],"concepts":[{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.9185401201248169},{"id":"https://openalex.org/C2780700455","wikidata":"https://www.wikidata.org/wiki/Q7236515","display_name":"Power gating","level":4,"score":0.8779186010360718},{"id":"https://openalex.org/C117551214","wikidata":"https://www.wikidata.org/wiki/Q6692774","display_name":"Low-power electronics","level":4,"score":0.5980286598205566},{"id":"https://openalex.org/C45872418","wikidata":"https://www.wikidata.org/wiki/Q5318966","display_name":"Dynamic demand","level":3,"score":0.5618466734886169},{"id":"https://openalex.org/C194544171","wikidata":"https://www.wikidata.org/wiki/Q21105679","display_name":"Gating","level":2,"score":0.5514720678329468},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.5403748750686646},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.49822115898132324},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4819228947162628},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4363314211368561},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.43013519048690796},{"id":"https://openalex.org/C57149124","wikidata":"https://www.wikidata.org/wiki/Q587346","display_name":"Sleep mode","level":4,"score":0.4177713096141815},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.39774033427238464},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3969497084617615},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.3698056936264038},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2815205752849579},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.21942946314811707},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.1460099220275879},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.1328868269920349},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C42407357","wikidata":"https://www.wikidata.org/wiki/Q521","display_name":"Physiology","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icta50426.2020.9332120","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icta50426.2020.9332120","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.9100000262260437,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1933280719","https://openalex.org/W2047299917","https://openalex.org/W2140493719","https://openalex.org/W2943764824","https://openalex.org/W3103339143"],"related_works":["https://openalex.org/W4386968318","https://openalex.org/W2474747038","https://openalex.org/W2524911825","https://openalex.org/W2052455055","https://openalex.org/W4232628459","https://openalex.org/W2001020839","https://openalex.org/W574669072","https://openalex.org/W2046826624","https://openalex.org/W2610873304","https://openalex.org/W2337711143"],"abstract_inverted_index":{"In":[0,30],"digital":[1],"circuits,":[2],"dynamic":[3],"power":[4,17,20,93],"consumption":[5,21],"caused":[6],"by":[7,26],"clock":[8],"switching":[9],"occupies":[10],"a":[11,33],"large":[12],"part":[13],"of":[14,80],"the":[15,51],"total":[16],"consumption.":[18],"Dynamic":[19],"can":[22,57],"be":[23,58],"effectively":[24],"reduced":[25],"using":[27],"clock-gating":[28,34],"technology.":[29],"this":[31,72],"work,":[32],"cell":[35,56,95],"is":[36,47,84,97],"proposed":[37,55],"with":[38,62],"sleeping":[39],"mechanism":[40],"under":[41],"0.7":[42],"V":[43],"supply.":[44],"Power":[45],"gating":[46],"used":[48,59],"to":[49,65,69],"decrease":[50],"static":[52],"power.":[53],"The":[54],"in":[60,88],"circuit":[61],"frequency":[63,90],"up":[64],"1MHz":[66],"typically.":[67],"Compared":[68],"existing":[70],"design,":[71],"work":[73],"stands":[74],"out":[75],"for":[76,86],"lower":[77],"leakage":[78],"current":[79],"1.56":[81],"pA,":[82],"which":[83],"suitable":[85],"circuits":[87],"low":[89,92],"where":[91],"standard":[94],"library":[96],"required.":[98]},"counts_by_year":[],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}