{"id":"https://openalex.org/W4404239415","doi":"https://doi.org/10.1109/icstcc62912.2024.10744648","title":"RiscDaqExt \u2013 Digital Acquisition and Control RISC-V Extension","display_name":"RiscDaqExt \u2013 Digital Acquisition and Control RISC-V Extension","publication_year":2024,"publication_date":"2024-10-10","ids":{"openalex":"https://openalex.org/W4404239415","doi":"https://doi.org/10.1109/icstcc62912.2024.10744648"},"language":"en","primary_location":{"id":"doi:10.1109/icstcc62912.2024.10744648","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/icstcc62912.2024.10744648","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 28th International Conference on System Theory, Control and Computing (ICSTCC)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5081657436","display_name":"Cosmin-Andrei Popovici","orcid":"https://orcid.org/0000-0002-9410-9343"},"institutions":[{"id":"https://openalex.org/I4210108695","display_name":"Gheorghe Asachi Technical University of Ia\u0219i","ror":"https://ror.org/014zxnz40","country_code":"RO","type":"education","lineage":["https://openalex.org/I4210108695"]}],"countries":["RO"],"is_corresponding":false,"raw_author_name":"Cosmin-Andrei Popovici","raw_affiliation_strings":["Technical University \"Gheorghe Asachi\",Faculty of Automatic Control and Computer Engineering,Department of Computer Engineering,Iași,România"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Technical University \"Gheorghe Asachi\",Faculty of Automatic Control and Computer Engineering,Department of Computer Engineering,Iași,România","institution_ids":["https://openalex.org/I4210108695"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084646497","display_name":"Andrei Stan","orcid":"https://orcid.org/0000-0002-4903-4119"},"institutions":[{"id":"https://openalex.org/I4210108695","display_name":"Gheorghe Asachi Technical University of Ia\u0219i","ror":"https://ror.org/014zxnz40","country_code":"RO","type":"education","lineage":["https://openalex.org/I4210108695"]}],"countries":["RO"],"is_corresponding":false,"raw_author_name":"Andrei Stan","raw_affiliation_strings":["Technical University \"Gheorghe Asachi\",Faculty of Automatic Control and Computer Engineering,Department of Computer Engineering,Iași,România"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Technical University \"Gheorghe Asachi\",Faculty of Automatic Control and Computer Engineering,Department of Computer Engineering,Iași,România","institution_ids":["https://openalex.org/I4210108695"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5024843075","display_name":"Vasile Manta","orcid":"https://orcid.org/0000-0002-5180-4151"},"institutions":[{"id":"https://openalex.org/I4210108695","display_name":"Gheorghe Asachi Technical University of Ia\u0219i","ror":"https://ror.org/014zxnz40","country_code":"RO","type":"education","lineage":["https://openalex.org/I4210108695"]}],"countries":["RO"],"is_corresponding":false,"raw_author_name":"Vasile-Ion Manta","raw_affiliation_strings":["Technical University \"Gheorghe Asachi\",Faculty of Automatic Control and Computer Engineering,Department of Computer Engineering,Iași,România"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Technical University \"Gheorghe Asachi\",Faculty of Automatic Control and Computer Engineering,Department of Computer Engineering,Iași,România","institution_ids":["https://openalex.org/I4210108695"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I4210108695"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"582","last_page":"587"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.779699981212616,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.779699981212616,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.7745000123977661,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.6966999769210815,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7271656394004822},{"id":"https://openalex.org/keywords/extension","display_name":"Extension (predicate logic)","score":0.620067298412323},{"id":"https://openalex.org/keywords/reduced-instruction-set-computing","display_name":"Reduced instruction set computing","score":0.5038413405418396},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.316125750541687},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.24572962522506714},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.21579793095588684}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7271656394004822},{"id":"https://openalex.org/C2778029271","wikidata":"https://www.wikidata.org/wiki/Q5421931","display_name":"Extension (predicate logic)","level":2,"score":0.620067298412323},{"id":"https://openalex.org/C126298526","wikidata":"https://www.wikidata.org/wiki/Q189376","display_name":"Reduced instruction set computing","level":3,"score":0.5038413405418396},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.316125750541687},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.24572962522506714},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.21579793095588684}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icstcc62912.2024.10744648","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/icstcc62912.2024.10744648","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 28th International Conference on System Theory, Control and Computing (ICSTCC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W998398075","https://openalex.org/W2963255460","https://openalex.org/W3002246177","https://openalex.org/W3135384844","https://openalex.org/W4308427914","https://openalex.org/W4316039847","https://openalex.org/W4321381226","https://openalex.org/W4388562300"],"related_works":["https://openalex.org/W4391375266","https://openalex.org/W2899084033","https://openalex.org/W2748952813","https://openalex.org/W2075768550","https://openalex.org/W3022218857","https://openalex.org/W2369178846","https://openalex.org/W2390279801","https://openalex.org/W2370289839","https://openalex.org/W4391913857","https://openalex.org/W2358668433"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,52,56,63,88,146,154,172,182,186],"RISC-V":[4,129],"extension,":[5],"called":[6],"RiscDaqExt":[7],"designed":[8],"for":[9,94,98],"Digital":[10],"Acquisition":[11],"and":[12,41,80,97,158],"Control":[13],"over":[14,166],"32":[15,104],"individually":[16],"managed":[17],"digital":[18,140,169],"channels.":[19],"Each":[20],"channel":[21],"can":[22,30,45],"be":[23,31,46],"configured":[24],"as":[25],"input":[26],"or":[27,33,62,115],"output,":[28],"inputs":[29,61],"negated":[32],"filtered":[34],"before":[35],"being":[36],"recorded":[37],"using":[38,87],"specific":[39],"masks":[40],"output":[42],"channels":[43],"source":[44],"chosen":[47],"between":[48],"values":[49,106],"given":[50],"with":[51,107,153,171],"mask,":[53],"result":[54,161],"of":[55,76,103,139,162],"multi-signal":[57],"operation":[58,164],"on":[59],"specified":[60],"PWM":[64],"signal":[65],"generated":[66],"by":[67],"the":[68,100,128,160],"SigWavy":[69],"extension.":[70],"The":[71,83,123],"extension":[72,84,91],"is":[73,85],"also":[74],"capable":[75],"measuring":[77],"PWMs":[78],"frequencies":[79],"duty":[81],"cycles.":[82],"controlled":[86],"dedicated":[89],"ISA":[90],"containing":[92],"instructions":[93],"setting/getting":[95],"configuration/values":[96],"controlling":[99],"storing":[101],"records":[102,141],"signals":[105],"32-bit":[108],"timestamps":[109],"to":[110,117,134],"an":[111,136],"attached":[112],"DDR3":[113],"memory":[114],"directly":[116],"hosting":[118],"PC\u2019s":[119],"RAM":[120],"via":[121],"Ethernet.":[122],"proposed":[124],"solution,":[125],"embedded":[126],"into":[127],"CPU":[130],"named":[131],"RiscDaq":[132],"manages":[133],"initiate":[135],"Ethernet":[137],"transmission":[138],"9.78x":[142],"times":[143,179,188],"faster":[144,180],"than":[145,181],"MicroBlaze":[147],"microcontroller,":[148],"although":[149],"our":[150],"SoC":[151],"operates":[152],"4x":[155],"lower":[156],"frequency,":[157],"outputs":[159],"logical":[163],"performed":[165],"maximum":[167],"31":[168],"channels,":[170],"constant":[173],"20":[174],"ns":[175],"propagation":[176],"delay,":[177],"49.2x":[178],"Cortex-M7":[183],"clocked":[184],"at":[185],"6x":[187],"higher":[189],"frequency.":[190]},"counts_by_year":[],"updated_date":"2026-07-15T18:14:33.161393","created_date":"2025-10-10T00:00:00"}