{"id":"https://openalex.org/W1997188504","doi":"https://doi.org/10.1109/icsamos.2010.5642098","title":"A library of dual-clock FIFOs for cost-effective and flexible MPSoC design","display_name":"A library of dual-clock FIFOs for cost-effective and flexible MPSoC design","publication_year":2010,"publication_date":"2010-07-01","ids":{"openalex":"https://openalex.org/W1997188504","doi":"https://doi.org/10.1109/icsamos.2010.5642098","mag":"1997188504"},"language":"en","primary_location":{"id":"doi:10.1109/icsamos.2010.5642098","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icsamos.2010.5642098","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5027446961","display_name":"Alessandro Strano","orcid":null},"institutions":[{"id":"https://openalex.org/I201324441","display_name":"University of Ferrara","ror":"https://ror.org/041zkgm14","country_code":"IT","type":"education","lineage":["https://openalex.org/I201324441"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Alessandro Strano","raw_affiliation_strings":["ENDIF, University of Ferrara, Ferrara, Italy","ENDIF, University of Ferrara, 44100 Ferrara, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ENDIF, University of Ferrara, Ferrara, Italy","institution_ids":["https://openalex.org/I201324441"]},{"raw_affiliation_string":"ENDIF, University of Ferrara, 44100 Ferrara, Italy","institution_ids":["https://openalex.org/I201324441"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010239929","display_name":"Daniele Ludovici","orcid":null},"institutions":[{"id":"https://openalex.org/I98358874","display_name":"Delft University of Technology","ror":"https://ror.org/02e2c7k09","country_code":"NL","type":"education","lineage":["https://openalex.org/I98358874"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"Daniele Ludovici","raw_affiliation_strings":["Computer Engineering Lab., Delft University of Technology, The Netherlands"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Engineering Lab., Delft University of Technology, The Netherlands","institution_ids":["https://openalex.org/I98358874"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5011268330","display_name":"Davide Bertozzi","orcid":"https://orcid.org/0000-0001-7462-4551"},"institutions":[{"id":"https://openalex.org/I201324441","display_name":"University of Ferrara","ror":"https://ror.org/041zkgm14","country_code":"IT","type":"education","lineage":["https://openalex.org/I201324441"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Davide Bertozzi","raw_affiliation_strings":["ENDIF, University of Ferrara, Ferrara, Italy","ENDIF, University of Ferrara, 44100 Ferrara, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ENDIF, University of Ferrara, Ferrara, Italy","institution_ids":["https://openalex.org/I201324441"]},{"raw_affiliation_string":"ENDIF, University of Ferrara, 44100 Ferrara, Italy","institution_ids":["https://openalex.org/I201324441"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":3.2272,"has_fulltext":false,"cited_by_count":25,"citation_normalized_percentile":{"value":0.92827173,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"20","last_page":"27"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/mpsoc","display_name":"MPSoC","score":0.8001595735549927},{"id":"https://openalex.org/keywords/synchronizer","display_name":"Synchronizer","score":0.693529486656189},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6779066324234009},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5480870604515076},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.4924543797969818},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.448417067527771},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3600222170352936},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.1806941032409668},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.12184971570968628},{"id":"https://openalex.org/keywords/channel","display_name":"Channel (broadcasting)","score":0.07775712013244629}],"concepts":[{"id":"https://openalex.org/C2777187653","wikidata":"https://www.wikidata.org/wiki/Q975106","display_name":"MPSoC","level":3,"score":0.8001595735549927},{"id":"https://openalex.org/C66727535","wikidata":"https://www.wikidata.org/wiki/Q7662199","display_name":"Synchronizer","level":2,"score":0.693529486656189},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6779066324234009},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5480870604515076},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.4924543797969818},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.448417067527771},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3600222170352936},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.1806941032409668},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.12184971570968628},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.07775712013244629}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/icsamos.2010.5642098","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icsamos.2010.5642098","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation","raw_type":"proceedings-article"},{"id":"pmh:oai:iris.unife.it:11392/1431312","is_oa":false,"landing_page_url":"http://hdl.handle.net/11392/1431312","pdf_url":null,"source":{"id":"https://openalex.org/S4306400369","display_name":"Institutional Research Information System University of Ferrara (University of Ferrara)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I201324441","host_organization_name":"University of Ferrara","host_organization_lineage":["https://openalex.org/I201324441"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1600358781","https://openalex.org/W2099034654","https://openalex.org/W2106910123","https://openalex.org/W2107295017","https://openalex.org/W2126647846","https://openalex.org/W2128773792","https://openalex.org/W2133027848","https://openalex.org/W2136011486","https://openalex.org/W2136692989","https://openalex.org/W2136994107","https://openalex.org/W2140427713","https://openalex.org/W2160104413","https://openalex.org/W2160642395","https://openalex.org/W2162867364","https://openalex.org/W2171940713","https://openalex.org/W3140430354","https://openalex.org/W3145659410","https://openalex.org/W6680198301"],"related_works":["https://openalex.org/W2392430353","https://openalex.org/W1976012348","https://openalex.org/W2614713859","https://openalex.org/W2002682434","https://openalex.org/W2137671689","https://openalex.org/W4387782849","https://openalex.org/W2113449380","https://openalex.org/W2012131147","https://openalex.org/W3146394219","https://openalex.org/W2502691491"],"abstract_inverted_index":{"Customization":[0],"of":[1,17,24,46,84,130,139,158,168],"IP":[2],"blocks":[3],"in":[4,95,147,177],"a":[5,26,49,67,72,82,165],"multi-processor":[6],"system-on-chip":[7],"(MPSoC)":[8],"is":[9,114],"the":[10,14,96,107,120,127,131,155,159,178],"historical":[11],"approach":[12],"to":[13,35,59,101,174],"cost-effective":[15,88],"implementation":[16,109],"such":[18],"systems.":[19],"A":[20],"recent":[21],"trend":[22],"consists":[23],"structuring":[25],"MPSoC":[27,89,181],"into":[28,119],"loosely":[29],"coupled":[30],"voltage":[31],"and":[32,62,76,123,172],"frequency":[33],"islands":[34,45],"meet":[36],"tight":[37],"power":[38,75],"budgets.":[39],"In":[40],"this":[41],"context,":[42],"synchronization":[43,132,141],"between":[44],"synchronicity":[47],"becomes":[48],"major":[50],"design":[51],"issue.":[52],"Dual-clock":[53],"FIFOs":[54,86],"compare":[55],"favorably":[56],"with":[57,154],"respect":[58],"synchronizer-based":[60],"designs":[61],"pausible":[63],"clocking":[64],"interfaces":[65],"from":[66],"performance":[68,128],"viewpoint,":[69],"but":[70,149],"incur":[71],"significant":[73],"area,":[74],"latency":[77],"overhead.":[78],"This":[79],"paper":[80],"proposes":[81],"library":[83,97,142],"dual-clock":[85],"for":[87,116],"design,":[90],"where":[91],"each":[92],"architecture":[93,122],"variant":[94],"has":[98],"been":[99,145,151],"designed":[100],"match":[102],"well-defined":[103],"operating":[104],"conditions":[105],"at":[106,134],"minimum":[108],"cost.":[110],"Each":[111],"FIFO":[112],"synchronizer":[113],"suitable":[115],"plug-and-play":[117],"insertion":[118],"NoC":[121],"selection":[124],"depends":[125],"on":[126],"requirements":[129],"interface":[133],"hand.":[135],"Above":[136],"all,":[137],"components":[138],"our":[140],"have":[143,150],"not":[144],"conceived":[146],"isolation,":[148],"tightly":[152],"co-designed":[153],"switching":[156],"fabric":[157],"on-chip":[160],"interconnection":[161],"network,":[162],"thus":[163],"making":[164],"conscious":[166],"use":[167],"power-hungry":[169],"buffering":[170],"resources":[171],"leading":[173],"affordable":[175],"implementations":[176],"resource":[179],"constrained":[180],"domain.":[182]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2014,"cited_by_count":5},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":5}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}