{"id":"https://openalex.org/W1978696200","doi":"https://doi.org/10.1109/icsamos.2010.5642093","title":"A fully programmable FSM-based Processing Engine for Gigabytes/s header parsing","display_name":"A fully programmable FSM-based Processing Engine for Gigabytes/s header parsing","publication_year":2010,"publication_date":"2010-07-01","ids":{"openalex":"https://openalex.org/W1978696200","doi":"https://doi.org/10.1109/icsamos.2010.5642093","mag":"1978696200"},"language":"en","primary_location":{"id":"doi:10.1109/icsamos.2010.5642093","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icsamos.2010.5642093","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5044511829","display_name":"Konstantin Septinus","orcid":null},"institutions":[{"id":"https://openalex.org/I4210145956","display_name":"Institut f\u00fcr Mikroelektronik- und Mechatronik-Systeme","ror":"https://ror.org/0445d9h15","country_code":"DE","type":"facility","lineage":["https://openalex.org/I4210145956"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Konstantin Septinus","raw_affiliation_strings":["Institute of Microelectronic Systems, Hanover, Germany","Institute of Microelectronic Systems, Appelstr. 4, 30167 Hannover, Germany"],"affiliations":[{"raw_affiliation_string":"Institute of Microelectronic Systems, Hanover, Germany","institution_ids":["https://openalex.org/I4210145956"]},{"raw_affiliation_string":"Institute of Microelectronic Systems, Appelstr. 4, 30167 Hannover, Germany","institution_ids":["https://openalex.org/I4210145956"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5050808949","display_name":"P. Pirsch","orcid":null},"institutions":[{"id":"https://openalex.org/I4210145956","display_name":"Institut f\u00fcr Mikroelektronik- und Mechatronik-Systeme","ror":"https://ror.org/0445d9h15","country_code":"DE","type":"facility","lineage":["https://openalex.org/I4210145956"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Peter Pirsch","raw_affiliation_strings":["Institute of Microelectronic Systems, Hanover, Germany","Institute of Microelectronic Systems, Appelstr. 4, 30167 Hannover, Germany"],"affiliations":[{"raw_affiliation_string":"Institute of Microelectronic Systems, Hanover, Germany","institution_ids":["https://openalex.org/I4210145956"]},{"raw_affiliation_string":"Institute of Microelectronic Systems, Appelstr. 4, 30167 Hannover, Germany","institution_ids":["https://openalex.org/I4210145956"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5016532646","display_name":"Holger Blume","orcid":"https://orcid.org/0000-0002-0640-6875"},"institutions":[{"id":"https://openalex.org/I4210145956","display_name":"Institut f\u00fcr Mikroelektronik- und Mechatronik-Systeme","ror":"https://ror.org/0445d9h15","country_code":"DE","type":"facility","lineage":["https://openalex.org/I4210145956"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Holger Blume","raw_affiliation_strings":["Institute of Microelectronic Systems, Hanover, Germany","Institute of Microelectronic Systems, Appelstr. 4, 30167 Hannover, Germany"],"affiliations":[{"raw_affiliation_string":"Institute of Microelectronic Systems, Hanover, Germany","institution_ids":["https://openalex.org/I4210145956"]},{"raw_affiliation_string":"Institute of Microelectronic Systems, Appelstr. 4, 30167 Hannover, Germany","institution_ids":["https://openalex.org/I4210145956"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5058592204","display_name":"U. Mayer","orcid":null},"institutions":[{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]},{"id":"https://openalex.org/I4210095996","display_name":"IBM (Germany)","ror":"https://ror.org/00pm7rm97","country_code":"DE","type":"company","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210095996"]}],"countries":["DE","US"],"is_corresponding":false,"raw_author_name":"Ulrich Mayer","raw_affiliation_strings":["IBM Deutschland Research and Development GmbH, Boeblingen, Germany","IBM Deutschland Research & Development GmbH Schoenaicher Str. 220, 71032 Boeblingen, Germany"],"affiliations":[{"raw_affiliation_string":"IBM Deutschland Research and Development GmbH, Boeblingen, Germany","institution_ids":["https://openalex.org/I4210095996"]},{"raw_affiliation_string":"IBM Deutschland Research & Development GmbH Schoenaicher Str. 220, 71032 Boeblingen, Germany","institution_ids":["https://openalex.org/I1341412227"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5044511829"],"corresponding_institution_ids":["https://openalex.org/I4210145956"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.06620411,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"45","last_page":"54"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11269","display_name":"Algorithms and Data Compression","score":0.9822999835014343,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9778000116348267,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8341914415359497},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.6574024558067322},{"id":"https://openalex.org/keywords/coprocessor","display_name":"Coprocessor","score":0.6198212504386902},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.5068700909614563},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.463181734085083},{"id":"https://openalex.org/keywords/header","display_name":"Header","score":0.45294660329818726},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.45035961270332336},{"id":"https://openalex.org/keywords/packet-processing","display_name":"Packet processing","score":0.43599462509155273},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.41876330971717834},{"id":"https://openalex.org/keywords/deep-packet-inspection","display_name":"Deep packet inspection","score":0.41798147559165955},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3624364137649536},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3407936692237854},{"id":"https://openalex.org/keywords/network-packet","display_name":"Network packet","score":0.2459414303302765},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.1509215533733368}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8341914415359497},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.6574024558067322},{"id":"https://openalex.org/C86111242","wikidata":"https://www.wikidata.org/wiki/Q859595","display_name":"Coprocessor","level":2,"score":0.6198212504386902},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.5068700909614563},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.463181734085083},{"id":"https://openalex.org/C48105269","wikidata":"https://www.wikidata.org/wiki/Q1141160","display_name":"Header","level":2,"score":0.45294660329818726},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.45035961270332336},{"id":"https://openalex.org/C2779581428","wikidata":"https://www.wikidata.org/wiki/Q7122997","display_name":"Packet processing","level":3,"score":0.43599462509155273},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.41876330971717834},{"id":"https://openalex.org/C204679922","wikidata":"https://www.wikidata.org/wiki/Q734252","display_name":"Deep packet inspection","level":3,"score":0.41798147559165955},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3624364137649536},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3407936692237854},{"id":"https://openalex.org/C158379750","wikidata":"https://www.wikidata.org/wiki/Q214111","display_name":"Network packet","level":2,"score":0.2459414303302765},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.1509215533733368},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icsamos.2010.5642093","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icsamos.2010.5642093","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320311826","display_name":"Chengdu University of Information Technology","ror":"https://ror.org/01yxwrh59"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W281821942","https://openalex.org/W1554765953","https://openalex.org/W1556003661","https://openalex.org/W1558097909","https://openalex.org/W1834037038","https://openalex.org/W1960771887","https://openalex.org/W1972216377","https://openalex.org/W1980768932","https://openalex.org/W2002703045","https://openalex.org/W2066787952","https://openalex.org/W2083240666","https://openalex.org/W2123698600","https://openalex.org/W2124171197","https://openalex.org/W2798774769","https://openalex.org/W3143248510","https://openalex.org/W4206787395","https://openalex.org/W4252202719"],"related_works":["https://openalex.org/W3175867593","https://openalex.org/W2904326537","https://openalex.org/W2080202421","https://openalex.org/W166608820","https://openalex.org/W4212842074","https://openalex.org/W4386875655","https://openalex.org/W2313462451","https://openalex.org/W2897477705","https://openalex.org/W2119461845","https://openalex.org/W2037047765"],"abstract_inverted_index":{"In":[0],"this":[1,35,216],"paper":[2],"we":[3],"discuss":[4],"a":[5,21,55,61,66,123,139,185,199,257],"new":[6],"architecture,":[7,27],"which":[8,176],"is":[9,98,147,177,217],"deployed":[10],"for":[11,34,75,89],"multi-standard":[12],"packet":[13,90],"inspection":[14],"and":[15,30,60,81,158,230,237],"basic":[16],"network":[17,23],"processing":[18],"tasks":[19],"in":[20,104,129,204,244],"high-performance":[22,260],"coprocessor.":[24],"Thereby,":[25],"concepts,":[26],"compiler":[28],"tool-chain":[29],"VLSI":[31,142],"area":[32],"estimation":[33],"programmable":[36,183,259],"finite":[37],"state":[38],"machine":[39],"based":[40],"(FSM-based)":[41],"Processing":[42],"Engine,":[43],"FPE,":[44],"are":[45],"presented.":[46],"The":[47,93],"microarchitecture":[48],"comprises":[49],"an":[50,101,178,212],"FSM-controlled":[51],"instruction":[52],"sequencing":[53],"mechanism,":[54],"novel":[56],"register":[57],"organization":[58,239],"scheme":[59],"short":[62],"pipeline":[63],"instead":[64],"of":[65,78,125,131,181,188,224,232,240,253],"typical":[67],"multi-staged":[68],"processor":[69,103],"pipeline.":[70],"This":[71],"introduces":[72],"several":[73],"advantages":[74,85,252],"efficient":[76],"handling":[77],"conditional":[79],"branches":[80],"small":[82],"look-ups.":[83],"Those":[84],"can":[86,191],"be":[87,192],"utilized":[88],"classification":[91],"applications.":[92],"FPE":[94,145,196,255],"data":[95],"path":[96],"performance":[97],"compared":[99],"to":[100,116,127,135,149,155,206],"ARM9-type":[102],"two":[105],"exemplary":[106],"header":[107,261],"parsing":[108,262],"kernels":[109],"from":[110],"the":[111,117,119,136,144,170,182,195,245,251,254],"\u201dCommBench\u201d":[112],"benchmark":[113],"suite.":[114],"According":[115],"results,":[118],"presented":[120],"engine":[121],"provides":[122],"speed-up":[124],"4":[126],"10":[128],"terms":[130],"required":[132],"computation":[133],"cycles":[134],"ARM9.":[137],"Using":[138],"65":[140],"nm":[141],"technology,":[143],"design":[146],"supposed":[148],"run":[150],"at":[151],"clock":[152],"frequencies":[153],"up":[154],"2":[156],"GHz":[157],"requires":[159,198],"about":[160],"1.8":[161],"mm":[162],"<sup":[163],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[164],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[165],"chip":[166],"area.":[167],"Based":[168],"on":[169],"specific":[171],"transition":[172],"rule":[173],"memory":[174,186],"organization,":[175],"essential":[179],"element":[180],"FSM,":[184],"utilization":[187],"around":[189],"95%":[190],"achieved.":[193],"However,":[194],"micro-architecture":[197],"customized":[200],"code":[201,210],"translation":[202],"chain":[203],"order":[205],"transfer":[207],"high-level":[208],"program":[209],"into":[211],"FSM":[213,242],"representation.":[214],"Basically,":[215],"achieved":[218],"by":[219],"three":[220],"steps:":[221],"(1)":[222],"generation":[223,231],"sequential,":[225],"assembly-like":[226],"macro-instructions,":[227],"(2)":[228],"scheduling":[229],"FSM-based":[233],"horizontal":[234],"(parallel)":[235],"micro-code":[236],"(3)":[238],"respective":[241],"rules":[243],"\u201dinstruction\u201d":[246],"memory.":[247],"Our":[248],"studies":[249],"confirm":[250],"as":[256],"fully":[258],"engine.":[263]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}