{"id":"https://openalex.org/W1965018796","doi":"https://doi.org/10.1109/icsamos.2008.4664839","title":"Towards unified mechanisms for inter-processor communication","display_name":"Towards unified mechanisms for inter-processor communication","publication_year":2008,"publication_date":"2008-07-01","ids":{"openalex":"https://openalex.org/W1965018796","doi":"https://doi.org/10.1109/icsamos.2008.4664839","mag":"1965018796"},"language":"en","primary_location":{"id":"doi:10.1109/icsamos.2008.4664839","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icsamos.2008.4664839","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5037481849","display_name":"Manolis Katevenis","orcid":"https://orcid.org/0009-0008-5437-4709"},"institutions":[{"id":"https://openalex.org/I142617266","display_name":"University of Crete","ror":"https://ror.org/00dr28g20","country_code":"GR","type":"education","lineage":["https://openalex.org/I142617266"]},{"id":"https://openalex.org/I8901234","display_name":"Foundation for Research and Technology Hellas","ror":"https://ror.org/052rphn09","country_code":"GR","type":"facility","lineage":["https://openalex.org/I8901234"]}],"countries":["GR"],"is_corresponding":true,"raw_author_name":"Manolis G.H. Katevenis","raw_affiliation_strings":["Department of Computer Science Heraklion, University of Crete, Crete, Greece","Inst. of Comput. Sci., Found. for Res. & Technol.-Hellas (FORTH), Heraklion"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science Heraklion, University of Crete, Crete, Greece","institution_ids":["https://openalex.org/I142617266"]},{"raw_affiliation_string":"Inst. of Comput. Sci., Found. for Res. & Technol.-Hellas (FORTH), Heraklion","institution_ids":["https://openalex.org/I8901234"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5037481849"],"corresponding_institution_ids":["https://openalex.org/I142617266","https://openalex.org/I8901234"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.04183546,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"iii","last_page":"iii"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9957000017166138,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8611141443252563},{"id":"https://openalex.org/keywords/instruction-prefetch","display_name":"Instruction prefetch","score":0.7045247554779053},{"id":"https://openalex.org/keywords/cache-coherence","display_name":"Cache coherence","score":0.5774509310722351},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.5060753226280212},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.49657493829727173},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.474112331867218},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.46812406182289124},{"id":"https://openalex.org/keywords/interfacing","display_name":"Interfacing","score":0.45204854011535645},{"id":"https://openalex.org/keywords/programmer","display_name":"Programmer","score":0.44186586141586304},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4061128497123718},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.38792264461517334},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.2886415719985962},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2395555078983307},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.19387295842170715},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.19031000137329102}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8611141443252563},{"id":"https://openalex.org/C133588205","wikidata":"https://www.wikidata.org/wiki/Q28455645","display_name":"Instruction prefetch","level":3,"score":0.7045247554779053},{"id":"https://openalex.org/C141917322","wikidata":"https://www.wikidata.org/wiki/Q1025017","display_name":"Cache coherence","level":5,"score":0.5774509310722351},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5060753226280212},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.49657493829727173},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.474112331867218},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.46812406182289124},{"id":"https://openalex.org/C2776303644","wikidata":"https://www.wikidata.org/wiki/Q1020499","display_name":"Interfacing","level":2,"score":0.45204854011535645},{"id":"https://openalex.org/C2778514511","wikidata":"https://www.wikidata.org/wiki/Q1374194","display_name":"Programmer","level":2,"score":0.44186586141586304},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4061128497123718},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.38792264461517334},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.2886415719985962},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2395555078983307},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.19387295842170715},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.19031000137329102},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icsamos.2008.4664839","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icsamos.2008.4664839","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.7400000095367432,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2140324148","https://openalex.org/W2121199344","https://openalex.org/W2285914869","https://openalex.org/W3117515082","https://openalex.org/W2113441357","https://openalex.org/W3022537591","https://openalex.org/W2126134823","https://openalex.org/W2167639078","https://openalex.org/W2379283503","https://openalex.org/W2141676084"],"abstract_inverted_index":{"Modern":[0],"processors":[1,14],"no":[2],"longer":[3],"work":[4],"mostly":[5],"in":[6,96,112,179,203],"isolation,":[7],"but":[8,171],"rather":[9],"communicate":[10],"continuously":[11],"with":[12,157,168],"peer":[13],"and":[15,71,194,218,222,226,237,261,272,279,297,311],"other":[16,110],"devices;":[17],"communication":[18,31],"is":[19,123],"now":[20],"at":[21,68,85],"least":[22],"as":[23,25,258,263],"important":[24],"computation.":[26],"Old":[27],"architectures":[28,58],"had":[29],"the":[30,37,43,50,55,62,66,78,90,109,113,119,134,180,212,216,224,230,235,239,276,305],"medium":[32],"-the":[33],"network-":[34],"far":[35],"from":[36],"processor,":[38],"interfacing":[39],"to":[40,60,65,75,255,274,301],"it":[41,267],"through":[42],"I/O":[44],"bus,":[45],"which":[46,98],"was":[47,52],"acceptable":[48],"when":[49,118,133],"network":[51,63,175,280],"slower":[53],"than":[54],"processor.":[56],"New":[57],"need":[59],"bring":[61],"close":[64],"processors,":[67],"a":[69,284,302],"latency":[70],"throughput":[72],"level":[73],"equal":[74],"that":[76,243,252],"of":[77,115,126,136,154,163,304],"cache":[79,277],"memories.":[80],"Coherent":[81],"caches":[82,156,260],"are":[83,141,197,253],"good":[84],"supporting":[86],"Implicit":[87],"Communication,":[88,117],"where":[89],"communicating":[91],"threads":[92],"do":[93,229],"not":[94],"know":[95],"advance":[97],"input":[99,120,217],"data":[100,121,139,220,236],"will":[101,291],"be":[102,270],"needed":[103],"or":[104,160],"who":[105],"produced":[106],"them.":[107],"On":[108],"hand,":[111],"cases":[114],"Explicit":[116],"set":[122,140],"known":[124],"ahead":[125],"time,":[127],"prefetching":[128],"yields":[129],"best":[130],"performance;":[131],"furthermore,":[132],"users-to-be":[135],"an":[137],"output":[138,219],"known,":[142],"eager":[143],"send":[144,184],"works":[145,150,186],"even":[146,198],"better.":[147],"Prefetching":[148],"(pull-communication)":[149],"either":[151],"on":[152,161],"top":[153,162],"coherent":[155,259],"prefetch":[158],"engines,":[159],"local":[164,249,264],"stores":[165],"(scratchpad":[166],"memories)":[167],"remote":[169,190],"DMA,":[170],"consumes":[172],"much":[173],"less":[174],"traffic":[176,193],"-hence":[177],"energy-":[178],"second":[181],"case.":[182],"Eager":[183],"(push-communications)":[185],"almost":[187],"only":[188,214],"using":[189],"DMA;":[191],"again,":[192],"energy":[195],"advantages":[196],"more":[199],"pronounced.":[200],"Recent":[201],"advances":[202],"parallel":[204],"programming":[205],"efficiently":[206,293],"support":[207,294],"explicit":[208,298],"communication,":[209,299],"by":[210,232],"letting":[211],"programmer":[213],"identify":[215],"sets,":[221],"having":[223],"compiler":[225],"runtime":[227],"system":[228],"rest":[231],"appropriately":[233],"placing":[234],"scheduling":[238],"transfers.":[240],"We":[241],"conclude":[242],"future":[244],"chip":[245],"multiprocessors":[246],"should":[247,268],"have":[248],"SRAM":[250],"blocks":[251],"configurable":[254],"operate":[256],"partly":[257,262],"(scratchpad)":[265],"memories;":[266],"then":[269],"possible":[271],"advantageous":[273],"merge":[275],"controller":[278],"interface":[281],"functions":[282],"into":[283],"single":[285],"unit.":[286],"These":[287],"combined":[288],"hardware":[289],"mechanisms":[290],"most":[292],"both":[295],"implicit":[296],"leading":[300],"unification":[303],"two":[306],"traditional":[307],"camps:":[308],"shared":[309],"memory":[310],"message":[312],"passing.":[313]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
