{"id":"https://openalex.org/W3009560002","doi":"https://doi.org/10.1109/icsai48974.2019.9010464","title":"VLSI Architecture of 36-Mode Reconfigurable FFT Hardware Chip with Newly-Developed 2D-FIFO Arrangement Structure","display_name":"VLSI Architecture of 36-Mode Reconfigurable FFT Hardware Chip with Newly-Developed 2D-FIFO Arrangement Structure","publication_year":2019,"publication_date":"2019-11-01","ids":{"openalex":"https://openalex.org/W3009560002","doi":"https://doi.org/10.1109/icsai48974.2019.9010464","mag":"3009560002"},"language":"en","primary_location":{"id":"doi:10.1109/icsai48974.2019.9010464","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icsai48974.2019.9010464","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 6th International Conference on Systems and Informatics (ICSAI)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5059414366","display_name":"Xin-Yu Shih","orcid":"https://orcid.org/0000-0002-9045-5847"},"institutions":[{"id":"https://openalex.org/I142974352","display_name":"National Sun Yat-sen University","ror":"https://ror.org/00mjawt10","country_code":"TW","type":"education","lineage":["https://openalex.org/I142974352"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Xin-Yu Shih","raw_affiliation_strings":["Department of Electrical Engineering, National Sun Yat-sen University, Taiwan, R.O.C"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Sun Yat-sen University, Taiwan, R.O.C","institution_ids":["https://openalex.org/I142974352"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5059414366"],"corresponding_institution_ids":["https://openalex.org/I142974352"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.20142693,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"999","last_page":"1003"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9922000169754028,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9911999702453613,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/fast-fourier-transform","display_name":"Fast Fourier transform","score":0.8488730192184448},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6936172246932983},{"id":"https://openalex.org/keywords/fifo","display_name":"FIFO (computing and electronics)","score":0.6473348140716553},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.630198061466217},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.6115627288818359},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5897329449653625},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.5684892535209656},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5363418459892273},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.43618905544281006},{"id":"https://openalex.org/keywords/split-radix-fft-algorithm","display_name":"Split-radix FFT algorithm","score":0.4227094054222107},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.41377994418144226},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.34953510761260986},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16108438372612},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.1509256362915039},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.11857497692108154},{"id":"https://openalex.org/keywords/fourier-transform","display_name":"Fourier transform","score":0.0998886227607727},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.07253414392471313}],"concepts":[{"id":"https://openalex.org/C75172450","wikidata":"https://www.wikidata.org/wiki/Q623950","display_name":"Fast Fourier transform","level":2,"score":0.8488730192184448},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6936172246932983},{"id":"https://openalex.org/C2777145635","wikidata":"https://www.wikidata.org/wiki/Q515636","display_name":"FIFO (computing and electronics)","level":2,"score":0.6473348140716553},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.630198061466217},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.6115627288818359},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5897329449653625},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.5684892535209656},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5363418459892273},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.43618905544281006},{"id":"https://openalex.org/C103755468","wikidata":"https://www.wikidata.org/wiki/Q17103599","display_name":"Split-radix FFT algorithm","level":5,"score":0.4227094054222107},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.41377994418144226},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.34953510761260986},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16108438372612},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.1509256362915039},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.11857497692108154},{"id":"https://openalex.org/C102519508","wikidata":"https://www.wikidata.org/wiki/Q6520159","display_name":"Fourier transform","level":2,"score":0.0998886227607727},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.07253414392471313},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C203024314","wikidata":"https://www.wikidata.org/wiki/Q1365258","display_name":"Fourier analysis","level":3,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C166386157","wikidata":"https://www.wikidata.org/wiki/Q1477735","display_name":"Short-time Fourier transform","level":4,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icsai48974.2019.9010464","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icsai48974.2019.9010464","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 6th International Conference on Systems and Informatics (ICSAI)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/4","score":0.5,"display_name":"Quality Education"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1923763959","https://openalex.org/W1996890064","https://openalex.org/W2025988951","https://openalex.org/W2063731653","https://openalex.org/W2083416315","https://openalex.org/W2116465952","https://openalex.org/W2144895495","https://openalex.org/W2324524642","https://openalex.org/W2336946788","https://openalex.org/W2512116931","https://openalex.org/W2586844779","https://openalex.org/W3121983873","https://openalex.org/W3179665138","https://openalex.org/W6640355072","https://openalex.org/W6798323681"],"related_works":["https://openalex.org/W2185259940","https://openalex.org/W2031343199","https://openalex.org/W2113951268","https://openalex.org/W2168413811","https://openalex.org/W4226515754","https://openalex.org/W2977460836","https://openalex.org/W2144412928","https://openalex.org/W2356814585","https://openalex.org/W2948041274","https://openalex.org/W2004315237"],"abstract_inverted_index":{"In":[0,40,63,88],"this":[1],"paper,":[2],"we":[3,95],"propose":[4],"a":[5,36,45,68,112],"reconfigurable":[6,47],"FFT":[7,19,33,43,61,86,108],"hardware":[8],"architecture":[9],"for":[10,83],"3GPP":[11],"LTE":[12],"systems,":[13],"supporting":[14],"up":[15],"to":[16,53,75,90],"36":[17,84],"different":[18,85],"sizes.":[20,87],"It":[21],"simultaneously":[22],"includes":[23],"various":[24],"mixed-":[25],"radix":[26],"combination":[27],"of":[28,58,115,126],"radix-2,":[29],"radix-3,":[30],"and":[31,80,121],"radix-5":[32],"operations":[34],"in":[35,129],"stand-alone":[37],"FFT-processing":[38],"chip.":[39,130],"the":[41,64,98],"main":[42],"-computing,":[44],"novel":[46],"processing":[48],"kernel":[49],"engine":[50],"is":[51,73],"developed":[52,107],"support":[54],"4":[55],"configuration":[56],"types":[57],"changeable":[59],"hybrid-radix":[60],"operations.":[62],"data":[65],"storage":[66],"aspect,":[67],"newly-developed":[69],"2D-FIFO":[70],"arrangement":[71],"structure":[72],"used":[74],"flexibly":[76],"handle":[77],"efficient":[78],"reading":[79],"writing":[81],"data-access":[82],"addition":[89],"FPGA":[91],"prototyping":[92],"design":[93],"approach,":[94],"also":[96],"provide":[97],"ASIC":[99],"implementation":[100],"by":[101],"TSMC":[102],"90-nm":[103],"CMOS":[104],"technology.":[105],"The":[106],"chip":[109],"only":[110],"has":[111],"core":[113],"area":[114],"1.416":[116],"mm2,":[117],"consuming":[118],"24.2":[119],"mW":[120],"reaching":[122],"maximum":[123],"operating":[124],"frequency":[125],"111.11":[127],"MHz":[128]},"counts_by_year":[{"year":2023,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
