{"id":"https://openalex.org/W3008214483","doi":"https://doi.org/10.1109/icsai48974.2019.9010251","title":"Simulation SPI+FLASH system based on FPGA","display_name":"Simulation SPI+FLASH system based on FPGA","publication_year":2019,"publication_date":"2019-11-01","ids":{"openalex":"https://openalex.org/W3008214483","doi":"https://doi.org/10.1109/icsai48974.2019.9010251","mag":"3008214483"},"language":"en","primary_location":{"id":"doi:10.1109/icsai48974.2019.9010251","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icsai48974.2019.9010251","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 6th International Conference on Systems and Informatics (ICSAI)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100649042","display_name":"Xiuli Yu","orcid":"https://orcid.org/0000-0003-4334-4412"},"institutions":[{"id":"https://openalex.org/I139759216","display_name":"Beijing University of Posts and Telecommunications","ror":"https://ror.org/04w9fbh59","country_code":"CN","type":"education","lineage":["https://openalex.org/I139759216"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Xiuli Yu","raw_affiliation_strings":["Beijing University of Posts and Telecommunications, BUPT, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Beijing University of Posts and Telecommunications, BUPT, Beijing, China","institution_ids":["https://openalex.org/I139759216"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101414467","display_name":"Bingqi Li","orcid":"https://orcid.org/0000-0002-9994-7346"},"institutions":[{"id":"https://openalex.org/I139759216","display_name":"Beijing University of Posts and Telecommunications","ror":"https://ror.org/04w9fbh59","country_code":"CN","type":"education","lineage":["https://openalex.org/I139759216"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Bingqi Li","raw_affiliation_strings":["Beijing University of Posts and Telecommunications, BUPT, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Beijing University of Posts and Telecommunications, BUPT, Beijing, China","institution_ids":["https://openalex.org/I139759216"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5100649042"],"corresponding_institution_ids":["https://openalex.org/I139759216"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.22032769,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"8","issue":null,"first_page":"719","last_page":"724"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12941","display_name":"Embedded Systems and FPGA Design","score":0.9409000277519226,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12941","display_name":"Embedded Systems and FPGA Design","score":0.9409000277519226,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9016000032424927,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/flash-memory-emulator","display_name":"Flash memory emulator","score":0.8587287664413452},{"id":"https://openalex.org/keywords/flash-file-system","display_name":"Flash file system","score":0.8128707408905029},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7953529357910156},{"id":"https://openalex.org/keywords/flash-memory","display_name":"Flash memory","score":0.6796155571937561},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6756843328475952},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6622303128242493},{"id":"https://openalex.org/keywords/flash","display_name":"Flash (photography)","score":0.592872142791748},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5787234902381897},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.5242621898651123},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.46489161252975464},{"id":"https://openalex.org/keywords/data-transmission","display_name":"Data transmission","score":0.45197463035583496},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.24577489495277405},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.22980010509490967},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.14790445566177368}],"concepts":[{"id":"https://openalex.org/C96535780","wikidata":"https://www.wikidata.org/wiki/Q5457561","display_name":"Flash memory emulator","level":5,"score":0.8587287664413452},{"id":"https://openalex.org/C27670709","wikidata":"https://www.wikidata.org/wiki/Q5457555","display_name":"Flash file system","level":4,"score":0.8128707408905029},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7953529357910156},{"id":"https://openalex.org/C2776531357","wikidata":"https://www.wikidata.org/wiki/Q174077","display_name":"Flash memory","level":2,"score":0.6796155571937561},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6756843328475952},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6622303128242493},{"id":"https://openalex.org/C2777526259","wikidata":"https://www.wikidata.org/wiki/Q221836","display_name":"Flash (photography)","level":2,"score":0.592872142791748},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5787234902381897},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.5242621898651123},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.46489161252975464},{"id":"https://openalex.org/C557945733","wikidata":"https://www.wikidata.org/wiki/Q389772","display_name":"Data transmission","level":2,"score":0.45197463035583496},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.24577489495277405},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.22980010509490967},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.14790445566177368},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/icsai48974.2019.9010251","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icsai48974.2019.9010251","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 6th International Conference on Systems and Informatics (ICSAI)","raw_type":"proceedings-article"},{"id":"mag:3091934353","is_oa":false,"landing_page_url":"https://jglobal.jst.go.jp/en/detail?JGLOBAL_ID=202002265467758939","pdf_url":null,"source":{"id":"https://openalex.org/S4306512817","display_name":"IEEE Conference Proceedings","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":null,"raw_source_name":"IEEE Conference Proceedings","raw_type":null}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":1,"referenced_works":["https://openalex.org/W2381071144"],"related_works":["https://openalex.org/W164278522","https://openalex.org/W1937038249","https://openalex.org/W2085734125","https://openalex.org/W1691732600","https://openalex.org/W2391055460","https://openalex.org/W2082353818","https://openalex.org/W2291767606","https://openalex.org/W2104588025","https://openalex.org/W2606330551","https://openalex.org/W2082238054"],"abstract_inverted_index":{"FLASH":[0,95,173,203],"is":[1,37,122,154,189,217],"called":[2],"flash":[3,44,56],"memory,":[4],"also":[5],"known":[6],"as":[7,46],"high-performance":[8],"non-volatile":[9],"memory.":[10],"It":[11],"combines":[12],"the":[13,53,59,69,104,115,158,193,202,207,210,214,223,233,236],"advantages":[14],"of":[15,33,55,68,72,90,103,119,160,226,235],"RAM":[16],"and":[17,24,83,109,135,152,170,178,181,199,219],"ROM":[18],"which":[19,100,156],"can":[20],"transfer":[21],"data":[22,26,78,182,198],"quickly":[23],"maintain":[25],"for":[27],"a":[28,47,88],"long":[29],"time":[30],"in":[31,58],"case":[32],"power":[34],"failure.":[35],"This":[36],"why":[38],"many":[39],"portable":[40],"digital":[41],"devices":[42],"select":[43],"memory":[45,57],"storage":[48],"medium.":[49],"In":[50,66,112],"recent":[51],"years,":[52],"role":[54],"embedded":[60],"field":[61],"has":[62],"become":[63],"increasingly":[64],"important.":[65],"view":[67],"existing":[70],"problems":[71],"FLASH,":[73],"including":[74],"slow":[75],"erasing,":[76],"difficult":[77],"tracking,":[79],"complicated":[80],"operation":[81,168],"commands":[82,169],"timing,":[84],"this":[85,113],"paper":[86],"proposes":[87],"method":[89],"realizing":[91],"analog":[92],"SPI":[93,211],"+":[94],"system":[96,145,204,237],"based":[97,147],"on":[98,138,148],"FPGA":[99,149,208],"takes":[101],"advantage":[102],"parallelism,":[105],"reconfiguration,":[106],"high":[107],"real-time":[108,215],"fast":[110],"speed.":[111],"paper,":[114],"DE10":[116],"development":[117,140],"board":[118],"ALTERA":[120],"company":[121],"used":[123,190],"to":[124,191,196,201,231],"simulate":[125,192],"MX25L3206E":[126],"chip":[127],"(SPI+FLASH":[128],"system)":[129],"with":[130,184],"Verilog":[131],"Hardware":[132],"Description":[133],"Language":[134],"finite-state":[136],"machine":[137],"QuartusII":[139],"platform.":[141],"Thus,":[142],"an":[143],"integrated":[144],"platform":[146],"simulation":[150],"SPI+FLASH":[151],"controller":[153],"established,":[155],"replaces":[157],"function":[159,238],"actual":[161],"SPI+FLASH.":[162],"The":[163],"main":[164],"work":[165],"includes":[166],"decoding":[167],"accurately":[171],"controlling":[172],"work,":[174],"designing":[175],"interface":[176],"timing":[177],"control":[179],"logic,":[180],"transmission":[183],"dual-port":[185],"RAM.":[186],"Then":[187],"STM32":[188],"host":[194],"MCU":[195],"send":[197],"instructions":[200],"simulated":[205],"by":[206,221],"through":[209],"interface.":[212],"Finally,":[213],"signal":[216],"captured":[218],"displayed":[220],"using":[222],"tool":[224],"software":[225],"Signal":[227],"TapII":[228],"Logic":[229],"Analyzer":[230],"achieve":[232],"purpose":[234],"test.":[239]},"counts_by_year":[{"year":2023,"cited_by_count":1}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}