{"id":"https://openalex.org/W2783891560","doi":"https://doi.org/10.1109/icsai.2017.8248381","title":"Pin multiplexing optimization in FPGA prototyping system","display_name":"Pin multiplexing optimization in FPGA prototyping system","publication_year":2017,"publication_date":"2017-11-01","ids":{"openalex":"https://openalex.org/W2783891560","doi":"https://doi.org/10.1109/icsai.2017.8248381","mag":"2783891560"},"language":"en","primary_location":{"id":"doi:10.1109/icsai.2017.8248381","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icsai.2017.8248381","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 4th International Conference on Systems and Informatics (ICSAI)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5075044428","display_name":"Zhaoxiang Zong","orcid":"https://orcid.org/0009-0009-0931-9986"},"institutions":[{"id":"https://openalex.org/I4210156189","display_name":"Shanghai Dianji University","ror":"https://ror.org/055fene14","country_code":"CN","type":"education","lineage":["https://openalex.org/I4210156189"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Zhaoxiang Zong","raw_affiliation_strings":["School of Electronics and Information, Shanghai Dianji University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"School of Electronics and Information, Shanghai Dianji University, Shanghai, China","institution_ids":["https://openalex.org/I4210156189"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5075044428"],"corresponding_institution_ids":["https://openalex.org/I4210156189"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.18843204,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"2013","issue":null,"first_page":"721","last_page":"725"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8686020374298096},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.7921321392059326},{"id":"https://openalex.org/keywords/fpga-prototype","display_name":"FPGA prototype","score":0.7281136512756348},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6952744126319885},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.6852336525917053},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6490094065666199},{"id":"https://openalex.org/keywords/handshake","display_name":"Handshake","score":0.5881018042564392},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5152273774147034},{"id":"https://openalex.org/keywords/time-division-multiplexing","display_name":"Time-division multiplexing","score":0.4915939271450043},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.36100566387176514},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.08786731958389282}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8686020374298096},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.7921321392059326},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.7281136512756348},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6952744126319885},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.6852336525917053},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6490094065666199},{"id":"https://openalex.org/C2778000800","wikidata":"https://www.wikidata.org/wiki/Q830043","display_name":"Handshake","level":3,"score":0.5881018042564392},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5152273774147034},{"id":"https://openalex.org/C50661577","wikidata":"https://www.wikidata.org/wiki/Q901831","display_name":"Time-division multiplexing","level":3,"score":0.4915939271450043},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.36100566387176514},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.08786731958389282},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icsai.2017.8248381","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icsai.2017.8248381","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 4th International Conference on Systems and Informatics (ICSAI)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320317527","display_name":"Shanghai DianJi University","ror":"https://ror.org/055fene14"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W2075490772","https://openalex.org/W2141024358","https://openalex.org/W2148658001","https://openalex.org/W2172229083","https://openalex.org/W3147395157"],"related_works":["https://openalex.org/W2108707960","https://openalex.org/W431360389","https://openalex.org/W1998182654","https://openalex.org/W2007173547","https://openalex.org/W2997602288","https://openalex.org/W2152649261","https://openalex.org/W200899231","https://openalex.org/W2356927082","https://openalex.org/W181065026","https://openalex.org/W2258948885"],"abstract_inverted_index":{"FPGA":[0,36,57],"partition":[1],"is":[2,24,40,67,84,121],"a":[3,8,71,102,113],"key":[4],"step":[5],"to":[6,18,86,93],"prototype":[7],"complex":[9],"ASIC":[10,88],"design":[11,89],"onto":[12],"multi-FPGA":[13,103],"system.":[14,59],"After":[15],"partitioning,":[16],"due":[17],"the":[19,34,51,55,61,77,80,94,118,134],"number":[20],"of":[21,29,54,117,133],"inter-FPGA":[22],"signals":[23],"much":[25,143],"greater":[26],"than":[27,138,145],"that":[28,45,130],"physical":[30],"connections":[31],"available":[32],"on":[33,70],"board,":[35],"pin":[37,46,64],"multiplexing":[38,47,65],"technique":[39],"then":[41],"introduced.":[42],"It's":[43],"believed":[44],"strategy":[48],"directly":[49],"affects":[50],"timing":[52,131],"performance":[53,116,132],"whole":[56],"prototyping":[58],"In":[60],"present":[62,119],"work,":[63],"optimization":[66],"implemented":[68],"based":[69],"new":[72],"proposed":[73],"system-synchronous":[74],"architecture.":[75],"At":[76],"same":[78],"time,":[79],"protocol":[81],"converter":[82],"module":[83],"developed":[85],"make":[87],"interface":[90],"more":[91,144],"compatible":[92],"different":[95],"handshake":[96],"protocols.":[97],"Experiments":[98],"are":[99],"done":[100],"in":[101],"board":[104],"with":[105,123],"two":[106,124],"test":[107],"pattern":[108],"SHR":[109],"and":[110,141],"PRBS.":[111],"As":[112],"result,":[114],"system":[115],"architecture":[120],"compared":[122],"traditional":[125],"methods.":[126],"Test":[127],"data":[128],"show":[129],"System-synchronous":[135],"approach":[136,140],"doubled":[137],"I/OSERDES":[139],"even":[142],"Logic":[146],"TDM.":[147]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2021,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}