{"id":"https://openalex.org/W4234695468","doi":"https://doi.org/10.1109/icpp.2004.1327958","title":"Architecture and implementation of chip multiprocessors: custom logic components and software for rapid prototyping","display_name":"Architecture and implementation of chip multiprocessors: custom logic components and software for rapid prototyping","publication_year":2004,"publication_date":"2004-01-01","ids":{"openalex":"https://openalex.org/W4234695468","doi":"https://doi.org/10.1109/icpp.2004.1327958"},"language":"en","primary_location":{"id":"doi:10.1109/icpp.2004.1327958","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icpp.2004.1327958","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Conference on Parallel Processing, 2004. ICPP 2004.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5020225856","display_name":"N. Manjikian","orcid":null},"institutions":[{"id":"https://openalex.org/I204722609","display_name":"Queen's University","ror":"https://ror.org/02y72wh86","country_code":"CA","type":"education","lineage":["https://openalex.org/I204722609"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"N. Manjikian","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Queen's University, Kingston, ONT, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Queen's University, Kingston, ONT, Canada","institution_ids":["https://openalex.org/I204722609"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100379969","display_name":"Jin Huang","orcid":"https://orcid.org/0000-0002-1803-7077"},"institutions":[{"id":"https://openalex.org/I204722609","display_name":"Queen's University","ror":"https://ror.org/02y72wh86","country_code":"CA","type":"education","lineage":["https://openalex.org/I204722609"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Huang Jin","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Queen's University, Kingston, ONT, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Queen's University, Kingston, ONT, Canada","institution_ids":["https://openalex.org/I204722609"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5029419937","display_name":"J. Reed","orcid":null},"institutions":[{"id":"https://openalex.org/I204722609","display_name":"Queen's University","ror":"https://ror.org/02y72wh86","country_code":"CA","type":"education","lineage":["https://openalex.org/I204722609"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"J. Reed","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Queen's University, Kingston, ONT, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Queen's University, Kingston, ONT, Canada","institution_ids":["https://openalex.org/I204722609"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5091084737","display_name":"N. Cordeiro","orcid":null},"institutions":[{"id":"https://openalex.org/I204722609","display_name":"Queen's University","ror":"https://ror.org/02y72wh86","country_code":"CA","type":"education","lineage":["https://openalex.org/I204722609"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"N. Cordeiro","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Queen's University, Kingston, ONT, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Queen's University, Kingston, ONT, Canada","institution_ids":["https://openalex.org/I204722609"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5020225856"],"corresponding_institution_ids":["https://openalex.org/I204722609"],"apc_list":null,"apc_paid":null,"fwci":0.5266,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.69620253,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"13","issue":null,"first_page":"483","last_page":"492 vol.1"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.749549388885498},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5976498126983643},{"id":"https://openalex.org/keywords/executable","display_name":"Executable","score":0.5869154930114746},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5714718699455261},{"id":"https://openalex.org/keywords/rapid-prototyping","display_name":"Rapid prototyping","score":0.4867746829986572},{"id":"https://openalex.org/keywords/software-prototyping","display_name":"Software prototyping","score":0.4654809832572937},{"id":"https://openalex.org/keywords/programmable-array-logic","display_name":"Programmable Array Logic","score":0.4641868472099304},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.4507380723953247},{"id":"https://openalex.org/keywords/simple-programmable-logic-device","display_name":"Simple programmable logic device","score":0.42530661821365356},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.33594247698783875},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.320157527923584},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2612650394439697},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.2378389537334442},{"id":"https://openalex.org/keywords/software-development","display_name":"Software development","score":0.20542773604393005},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.18896636366844177},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12334951758384705}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.749549388885498},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5976498126983643},{"id":"https://openalex.org/C160145156","wikidata":"https://www.wikidata.org/wiki/Q778586","display_name":"Executable","level":2,"score":0.5869154930114746},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5714718699455261},{"id":"https://openalex.org/C2780395129","wikidata":"https://www.wikidata.org/wiki/Q1128971","display_name":"Rapid prototyping","level":2,"score":0.4867746829986572},{"id":"https://openalex.org/C2776697782","wikidata":"https://www.wikidata.org/wiki/Q576460","display_name":"Software prototyping","level":4,"score":0.4654809832572937},{"id":"https://openalex.org/C113323844","wikidata":"https://www.wikidata.org/wiki/Q1378651","display_name":"Programmable Array Logic","level":5,"score":0.4641868472099304},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.4507380723953247},{"id":"https://openalex.org/C34370810","wikidata":"https://www.wikidata.org/wiki/Q3961319","display_name":"Simple programmable logic device","level":5,"score":0.42530661821365356},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.33594247698783875},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.320157527923584},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2612650394439697},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.2378389537334442},{"id":"https://openalex.org/C529173508","wikidata":"https://www.wikidata.org/wiki/Q638608","display_name":"Software development","level":3,"score":0.20542773604393005},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.18896636366844177},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12334951758384705},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icpp.2004.1327958","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icpp.2004.1327958","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Conference on Parallel Processing, 2004. ICPP 2004.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1567646530","https://openalex.org/W1605442146","https://openalex.org/W2029171059","https://openalex.org/W2032094184","https://openalex.org/W2038724983","https://openalex.org/W2050487400","https://openalex.org/W2054496292","https://openalex.org/W2145163878","https://openalex.org/W2149811350","https://openalex.org/W2150121003","https://openalex.org/W2159903140","https://openalex.org/W3148484433","https://openalex.org/W6793277613","https://openalex.org/W7023539959"],"related_works":["https://openalex.org/W2197466303","https://openalex.org/W1512285683","https://openalex.org/W2187918628","https://openalex.org/W2151236218","https://openalex.org/W4234601000","https://openalex.org/W2534453537","https://openalex.org/W1607849496","https://openalex.org/W2147419146","https://openalex.org/W2139569078","https://openalex.org/W2254425074"],"abstract_inverted_index":{"This":[0],"work":[1],"describes":[2],"components":[3,63,140],"and":[4,28,40,68,79,89,117,137,141,152],"software":[5,103,114],"tools":[6,104],"in":[7,12,34,53,123],"support":[8],"of":[9,32,59,101,154],"rapid":[10,72],"prototyping":[11],"programmable":[13,21,35],"logic":[14,22,27,36,62,148],"for":[15,71,105,115],"research":[16,93],"on":[17],"chip":[18,45,120,143,149],"multiprocessors.":[19],"Contemporary":[20],"chips":[23,37],"offer":[24],"considerable":[25],"on-chip":[26],"memory":[29],"resources.":[30],"Prototyping":[31],"systems":[33],"is":[38,51,56,98,112],"faster":[39],"less":[41],"costly":[42],"than":[43],"full-custom":[44],"design.":[46],"The":[47,95,109],"first":[48],"contribution":[49,97,111],"that":[50,64],"described":[52],"this":[54,131],"paper":[55,132],"a":[57,99],"collection":[58],"original":[60,77],"research-oriented":[61],"provides":[65,133],"processor,":[66],"memory,":[67],"interconnect":[69],"functionality":[70],"prototyping.":[73],"Because":[74],"these":[75,129],"are":[76],"components,":[78,83],"not":[80],"proprietary":[81],"vendor-supplied":[82],"they":[84],"may":[85],"be":[86],"arbitrarily":[87],"extended":[88],"modified":[90],"to":[91,127],"suit":[92],"needs.":[94],"second":[96],"set":[100],"enhanced":[102],"generating":[106],"executable":[107],"code.":[108],"third":[110],"user-configurable":[113],"testing":[116,138],"evaluating":[118],"prototype":[119,139],"multiprocessor":[121],"implementations":[122],"hardware.":[124],"In":[125],"addition":[126],"describing":[128],"contributions,":[130],"results":[134],"from":[135],"implementing":[136],"complete":[142],"multiprocessors,":[144],"including":[145],"simulation":[146],"waveforms,":[147],"resource":[150],"utilization,":[151],"observations":[153],"hardware":[155],"operation.":[156]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}