{"id":"https://openalex.org/W4248727508","doi":"https://doi.org/10.1109/icpp.2004.1327935","title":"Architectural characterization of an XML-centric commercial server workload","display_name":"Architectural characterization of an XML-centric commercial server workload","publication_year":2004,"publication_date":"2004-01-01","ids":{"openalex":"https://openalex.org/W4248727508","doi":"https://doi.org/10.1109/icpp.2004.1327935"},"language":"en","primary_location":{"id":"doi:10.1109/icpp.2004.1327935","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icpp.2004.1327935","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Conference on Parallel Processing, 2004. ICPP 2004.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5032423786","display_name":"Padma Apparao","orcid":null},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Padma Apparao","raw_affiliation_strings":["Intel Corporation"],"affiliations":[{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111987814","display_name":"Ravi Iyer","orcid":null},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Ravi Iyer","raw_affiliation_strings":["Intel Corporation"],"affiliations":[{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5017093632","display_name":"R. Morin","orcid":null},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"R. Morin","raw_affiliation_strings":["Intel Corporation"],"affiliations":[{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066426418","display_name":"Naren Nayak","orcid":null},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Naren Nayak","raw_affiliation_strings":["Intel Corporation"],"affiliations":[{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110898494","display_name":"Mahesh Bhat","orcid":null},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Mahesh Bhat","raw_affiliation_strings":["Intel Corporation"],"affiliations":[{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5021464389","display_name":"D. Halliwell","orcid":null},"institutions":[{"id":"https://openalex.org/I2802755631","display_name":"Morgan Stanley (United States)","ror":"https://ror.org/00aphdz18","country_code":"US","type":"company","lineage":["https://openalex.org/I2802755631"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"D. Halliwell","raw_affiliation_strings":["Morgan Stanley"],"affiliations":[{"raw_affiliation_string":"Morgan Stanley","institution_ids":["https://openalex.org/I2802755631"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5076301795","display_name":"W. Steinberg","orcid":null},"institutions":[{"id":"https://openalex.org/I2802755631","display_name":"Morgan Stanley (United States)","ror":"https://ror.org/00aphdz18","country_code":"US","type":"company","lineage":["https://openalex.org/I2802755631"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"W. Steinberg","raw_affiliation_strings":["Morgan Stanley"],"affiliations":[{"raw_affiliation_string":"Morgan Stanley","institution_ids":["https://openalex.org/I2802755631"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5032423786"],"corresponding_institution_ids":["https://openalex.org/I4210158342"],"apc_list":null,"apc_paid":null,"fwci":0.49096078,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.67678471,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"292","last_page":"300 vol.1"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10101","display_name":"Cloud Computing and Resource Management","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8807196617126465},{"id":"https://openalex.org/keywords/xml","display_name":"XML","score":0.6236121654510498},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.5957649946212769},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.43741369247436523},{"id":"https://openalex.org/keywords/java","display_name":"Java","score":0.42016854882240295},{"id":"https://openalex.org/keywords/multithreading","display_name":"Multithreading","score":0.41895318031311035},{"id":"https://openalex.org/keywords/database","display_name":"Database","score":0.387408971786499},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3255205750465393},{"id":"https://openalex.org/keywords/thread","display_name":"Thread (computing)","score":0.19436991214752197}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8807196617126465},{"id":"https://openalex.org/C8797682","wikidata":"https://www.wikidata.org/wiki/Q2115","display_name":"XML","level":2,"score":0.6236121654510498},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.5957649946212769},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.43741369247436523},{"id":"https://openalex.org/C548217200","wikidata":"https://www.wikidata.org/wiki/Q251","display_name":"Java","level":2,"score":0.42016854882240295},{"id":"https://openalex.org/C201410400","wikidata":"https://www.wikidata.org/wiki/Q1064412","display_name":"Multithreading","level":3,"score":0.41895318031311035},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.387408971786499},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3255205750465393},{"id":"https://openalex.org/C138101251","wikidata":"https://www.wikidata.org/wiki/Q213092","display_name":"Thread (computing)","level":2,"score":0.19436991214752197}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icpp.2004.1327935","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icpp.2004.1327935","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Conference on Parallel Processing, 2004. ICPP 2004.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.47999998927116394,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W78537038","https://openalex.org/W1479787790","https://openalex.org/W1823898179","https://openalex.org/W1973190970","https://openalex.org/W1982752205","https://openalex.org/W1998289328","https://openalex.org/W2111742517","https://openalex.org/W2116020886","https://openalex.org/W2132560950","https://openalex.org/W2135102985","https://openalex.org/W2165755248","https://openalex.org/W3150160382","https://openalex.org/W4243587504","https://openalex.org/W6603177645","https://openalex.org/W6628765812","https://openalex.org/W6676737481","https://openalex.org/W6679745300"],"related_works":["https://openalex.org/W1940589050","https://openalex.org/W2355721938","https://openalex.org/W2387608311","https://openalex.org/W2973764441","https://openalex.org/W2086248387","https://openalex.org/W2350798290","https://openalex.org/W1542759904","https://openalex.org/W2378658106","https://openalex.org/W2185513608","https://openalex.org/W2373523640"],"abstract_inverted_index":{"As":[0],"XML":[1,160],"(extensible":[2],"markup":[3],"language)":[4],"rapidly":[5],"emerges":[6],"as":[7,45,98,166],"the":[8,76,87,94,127,152,159],"standard":[9],"for":[10,176],"information":[11,153],"storage":[12],"and":[13,24,75,110,139,146,163],"communication,":[14],"it":[15],"becomes":[16],"increasingly":[17],"important":[18],"to":[19,33,126,143,171],"understand":[20],"its":[21],"architectural":[22,95],"characteristics":[23,74,96,125,162],"performance":[25,82,119],"implications.":[26],"In":[27],"This":[28],"work,":[29],"our":[30],"goal":[31],"is":[32],"characterize":[34],"a":[35,40,60,167],"representative":[36],"XML-based":[37,62],"server":[38,58,63],"in":[39,157],"managed":[41],"runtime":[42],"environment":[43],"such":[44],"Java.":[46],"Based":[47],"on":[48,51,86],"detailed":[49],"measurements":[50],"an":[52,91],"Intel/spl":[53,116],"reg/":[54,117],"XeonTM":[55],"processor-based":[56],"commercial":[57],"running":[59],"real-world":[61],"workload,":[64],"we":[65,89,121],"start":[66],"by":[67],"looking":[68],"at":[69],"symmetric":[70],"multiprocessor":[71],"(SMP)":[72],"scaling":[73],"benefits":[77],"of":[78,93,130],"hyper-threading":[79],"technology.":[80],"Using":[81,112],"monitoring":[83],"events":[84],"provided":[85],"processor,":[88],"present":[90],"overview":[92],"(such":[97],"clocks":[99],"per":[100],"instruction":[101],"(CPI),":[102],"cache":[103],"miss":[104],"rates,":[105],"memory/bus":[106],"utilization,":[107],"branch":[108],"behavior":[109],"efficiency).":[111],"profiling":[113],"tools":[114],"like":[115],"VTuneTM":[118],"analyzer,":[120],"map":[122],"these":[123],"architectural/performance":[124],"various":[128],"components":[129],"application":[131,147],"execution":[132],"-":[133],"helping":[134],"us":[135],"identify":[136],"hot":[137],"spots":[138],"propose":[140],"potential":[141,173],"enhancements":[142],"code":[144],"generation":[145],"software.":[148],"We":[149],"believe":[150],"that":[151],"presented":[154],"Are":[155],"useful":[156,168],"understanding":[158],"processing":[161],"may":[164],"serve":[165],"first":[169],"step":[170],"identifying":[172],"hardware/software":[174],"optimizations":[175],"improved":[177],"future":[178],"performance.":[179]},"counts_by_year":[{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
