{"id":"https://openalex.org/W2171205966","doi":"https://doi.org/10.1109/icpads.2007.4447766","title":"Effect of number of faults on NoC power and performance","display_name":"Effect of number of faults on NoC power and performance","publication_year":2007,"publication_date":"2007-12-01","ids":{"openalex":"https://openalex.org/W2171205966","doi":"https://doi.org/10.1109/icpads.2007.4447766","mag":"2171205966"},"language":"en","primary_location":{"id":"doi:10.1109/icpads.2007.4447766","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icpads.2007.4447766","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 International Conference on Parallel and Distributed Systems","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5039329776","display_name":"Mahdiar Ghadiry","orcid":null},"institutions":[{"id":"https://openalex.org/I110525433","display_name":"Islamic Azad University, Tehran","ror":"https://ror.org/01kzn7k21","country_code":"IR","type":"education","lineage":["https://openalex.org/I110525433"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"M.H. Ghadiry","raw_affiliation_strings":["Department of Computer Engineering, Islamic Azad University, Iran"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, Islamic Azad University, Iran","institution_ids":["https://openalex.org/I110525433"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060342217","display_name":"Mahdieh Nadi","orcid":"https://orcid.org/0000-0002-1570-2879"},"institutions":[{"id":"https://openalex.org/I110525433","display_name":"Islamic Azad University, Tehran","ror":"https://ror.org/01kzn7k21","country_code":"IR","type":"education","lineage":["https://openalex.org/I110525433"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"M. Nadi","raw_affiliation_strings":["Department of Computer Engineering, Islamic Azad University, Iran"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, Islamic Azad University, Iran","institution_ids":["https://openalex.org/I110525433"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081696451","display_name":"Mohammad Taghi Manzuri","orcid":"https://orcid.org/0000-0002-3451-0338"},"institutions":[{"id":"https://openalex.org/I133529467","display_name":"Sharif University of Technology","ror":"https://ror.org/024c2fq17","country_code":"IR","type":"education","lineage":["https://openalex.org/I133529467"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"M.T. Manzuri-Shalmani","raw_affiliation_strings":["Department of Computer Engineering, Sharif University of Technology, Tehran, Iran"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, Sharif University of Technology, Tehran, Iran","institution_ids":["https://openalex.org/I133529467"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5043762973","display_name":"Dara Rahmati","orcid":"https://orcid.org/0000-0003-0104-4016"},"institutions":[{"id":"https://openalex.org/I133529467","display_name":"Sharif University of Technology","ror":"https://ror.org/024c2fq17","country_code":"IR","type":"education","lineage":["https://openalex.org/I133529467"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"D. Rahmati","raw_affiliation_strings":["Department of Computer Engineering, Sharif University of Technology, Tehran, Iran"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, Sharif University of Technology, Tehran, Iran","institution_ids":["https://openalex.org/I133529467"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":"42","issue":null,"first_page":"1","last_page":"9"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9961000084877014,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9940000176429749,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6994779706001282},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.6861721277236938},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.6854313015937805},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5725561380386353},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5624872446060181},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5375226736068726},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5135502815246582},{"id":"https://openalex.org/keywords/router","display_name":"Router","score":0.4903738498687744},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.45308154821395874},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4451358914375305},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.42966118454933167},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.33984965085983276},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2927864193916321},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.23348677158355713},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.16682860255241394}],"concepts":[{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6994779706001282},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.6861721277236938},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.6854313015937805},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5725561380386353},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5624872446060181},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5375226736068726},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5135502815246582},{"id":"https://openalex.org/C2775896111","wikidata":"https://www.wikidata.org/wiki/Q642560","display_name":"Router","level":2,"score":0.4903738498687744},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.45308154821395874},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4451358914375305},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.42966118454933167},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.33984965085983276},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2927864193916321},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.23348677158355713},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.16682860255241394},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icpads.2007.4447766","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icpads.2007.4447766","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 International Conference on Parallel and Distributed Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.6299999952316284}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":28,"referenced_works":["https://openalex.org/W17482347","https://openalex.org/W1643664389","https://openalex.org/W1835615008","https://openalex.org/W1994221466","https://openalex.org/W2051265155","https://openalex.org/W2082098861","https://openalex.org/W2097565437","https://openalex.org/W2100006166","https://openalex.org/W2102387714","https://openalex.org/W2114034686","https://openalex.org/W2119922166","https://openalex.org/W2123184444","https://openalex.org/W2123512296","https://openalex.org/W2129307244","https://openalex.org/W2138444824","https://openalex.org/W2146673261","https://openalex.org/W2155388085","https://openalex.org/W2156677140","https://openalex.org/W2158051804","https://openalex.org/W2228418281","https://openalex.org/W2554621958","https://openalex.org/W4205608751","https://openalex.org/W4235990555","https://openalex.org/W4285719527","https://openalex.org/W6663206060","https://openalex.org/W6675224354","https://openalex.org/W6677713047","https://openalex.org/W6805453576"],"related_works":["https://openalex.org/W2127180614","https://openalex.org/W2052816277","https://openalex.org/W2167988973","https://openalex.org/W2603824091","https://openalex.org/W2018755015","https://openalex.org/W2167711148","https://openalex.org/W4235531327","https://openalex.org/W1603115038","https://openalex.org/W2177095534","https://openalex.org/W1964344619"],"abstract_inverted_index":{"According":[0],"to":[1,84],"international":[2],"technology":[3],"roadmap":[4],"for":[5],"semiconductors":[6],"(ITRS),":[7],"before":[8],"the":[9,18,32,48,71,91],"end":[10],"of":[11,20,34,43,50,59,93,102,121],"this":[12,87],"decade,":[13],"we":[14,89],"will":[15],"be":[16,76],"entering":[17],"era":[19],"a":[21,25,38,116],"billion":[22,35],"transistors":[23],"on":[24,37,52,98],"single":[26],"chip.":[27],"The":[28],"major":[29,72],"threat":[30],"toward":[31],"achievement":[33],"transistor":[36],"chip":[39,53],"is":[40],"poor":[41],"scalability":[42],"current":[44],"interconnect":[45],"infrastructure.":[46],"With":[47],"advent":[49],"\"network":[51],"(NoC)\"":[54],"various":[55],"characters":[56],"and":[57,68,96,100,113],"methodologies":[58],"traditional":[60,81],"networks":[61,83],"were":[62],"hardly":[63],"considered":[64,77],"on-chip.":[65],"Failure,":[66],"power":[67,99],"area":[69],"are":[70],"concepts":[73],"that":[74],"should":[75],"when":[78],"migrating":[79],"from":[80],"interconnection":[82],"NoCs.":[85],"In":[86],"paper":[88],"study":[90],"effects":[92],"faulty":[94],"links":[95],"nodes":[97],"performance":[101],"mesh":[103],"based":[104],"NoC,":[105],"Also":[106],"several":[107],"routing":[108],"algorithms":[109],"have":[110],"been":[111],"implemented":[112],"simulated":[114],"using":[115],"cycle":[117],"accurate":[118],"VHDL":[119],"model":[120],"NoC.":[122]},"counts_by_year":[{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}