{"id":"https://openalex.org/W2161957081","doi":"https://doi.org/10.1109/icpads.2002.1183382","title":"Organization of shared memory with synchronization for multiprocessor-on-a-chip","display_name":"Organization of shared memory with synchronization for multiprocessor-on-a-chip","publication_year":2003,"publication_date":"2003-06-26","ids":{"openalex":"https://openalex.org/W2161957081","doi":"https://doi.org/10.1109/icpads.2002.1183382","mag":"2161957081"},"language":"en","primary_location":{"id":"doi:10.1109/icpads.2002.1183382","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icpads.2002.1183382","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Ninth International Conference on Parallel and Distributed Systems, 2002. Proceedings.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5075659609","display_name":"Akira Yamawaki","orcid":"https://orcid.org/0000-0002-8723-0620"},"institutions":[{"id":"https://openalex.org/I207014233","display_name":"Kyushu Institute of Technology","ror":"https://ror.org/02278tr80","country_code":"JP","type":"education","lineage":["https://openalex.org/I207014233"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"A. Yamawaki","raw_affiliation_strings":["Department of Electrical Engineering, Kyushu Institute of Technology, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Kyushu Institute of Technology, Japan","institution_ids":["https://openalex.org/I207014233"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5071214096","display_name":"Masahiko Iwane","orcid":null},"institutions":[{"id":"https://openalex.org/I207014233","display_name":"Kyushu Institute of Technology","ror":"https://ror.org/02278tr80","country_code":"JP","type":"education","lineage":["https://openalex.org/I207014233"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"M. Iwane","raw_affiliation_strings":["Department of Electrical Engineering, Kyushu Institute of Technology, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Kyushu Institute of Technology, Japan","institution_ids":["https://openalex.org/I207014233"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.2477,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.58748129,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"j84 d i","issue":null,"first_page":"83","last_page":"90"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.817712664604187},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.7796465754508972},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.7188540697097778},{"id":"https://openalex.org/keywords/mesi-protocol","display_name":"MESI protocol","score":0.6204963326454163},{"id":"https://openalex.org/keywords/cache-pollution","display_name":"Cache pollution","score":0.6070483922958374},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.6036507487297058},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.5927729606628418},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.5435358285903931},{"id":"https://openalex.org/keywords/cache-invalidation","display_name":"Cache invalidation","score":0.5176511406898499},{"id":"https://openalex.org/keywords/cache-coherence","display_name":"Cache coherence","score":0.5163487195968628},{"id":"https://openalex.org/keywords/smart-cache","display_name":"Smart Cache","score":0.5067992806434631},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.4856818616390228},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.4371318817138672},{"id":"https://openalex.org/keywords/thread","display_name":"Thread (computing)","score":0.4242831766605377},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3960832357406616},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.3783709406852722},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3461844325065613},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.22877228260040283},{"id":"https://openalex.org/keywords/channel","display_name":"Channel (broadcasting)","score":0.06989312171936035},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.06792658567428589}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.817712664604187},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.7796465754508972},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.7188540697097778},{"id":"https://openalex.org/C120936851","wikidata":"https://www.wikidata.org/wiki/Q1408065","display_name":"MESI protocol","level":5,"score":0.6204963326454163},{"id":"https://openalex.org/C113166858","wikidata":"https://www.wikidata.org/wiki/Q5015981","display_name":"Cache pollution","level":5,"score":0.6070483922958374},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.6036507487297058},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.5927729606628418},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.5435358285903931},{"id":"https://openalex.org/C25536678","wikidata":"https://www.wikidata.org/wiki/Q5015977","display_name":"Cache invalidation","level":5,"score":0.5176511406898499},{"id":"https://openalex.org/C141917322","wikidata":"https://www.wikidata.org/wiki/Q1025017","display_name":"Cache coherence","level":5,"score":0.5163487195968628},{"id":"https://openalex.org/C167713795","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"Smart Cache","level":5,"score":0.5067992806434631},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.4856818616390228},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.4371318817138672},{"id":"https://openalex.org/C138101251","wikidata":"https://www.wikidata.org/wiki/Q213092","display_name":"Thread (computing)","level":2,"score":0.4242831766605377},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3960832357406616},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.3783709406852722},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3461844325065613},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.22877228260040283},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.06989312171936035},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.06792658567428589}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icpads.2002.1183382","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icpads.2002.1183382","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Ninth International Conference on Parallel and Distributed Systems, 2002. Proceedings.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.6399999856948853,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W239283595","https://openalex.org/W1520460310","https://openalex.org/W1986804682","https://openalex.org/W2029171059","https://openalex.org/W2060601499","https://openalex.org/W2109502721","https://openalex.org/W2114421447","https://openalex.org/W2155373852","https://openalex.org/W2169539335","https://openalex.org/W2294693415","https://openalex.org/W4243834914","https://openalex.org/W4254064928","https://openalex.org/W6665373198","https://openalex.org/W6682805929","https://openalex.org/W6684584927"],"related_works":["https://openalex.org/W4312759433","https://openalex.org/W2584505417","https://openalex.org/W273173017","https://openalex.org/W1521238853","https://openalex.org/W2290179447","https://openalex.org/W2184371594","https://openalex.org/W2148571123","https://openalex.org/W4304166325","https://openalex.org/W2801630946","https://openalex.org/W2135365633"],"abstract_inverted_index":{"The":[0,19,38,57,76,137],"TSVM":[1,21,26,142],"is":[2,22,62],"a":[3,8,12,15,30,34,42,63,67,83,94,97],"logical":[4],"structured":[5],"memory":[6,32],"with":[7,82,99],"synchronization":[9],"to":[10,113],"improve":[11],"performance":[13],"in":[14,33,41],"multi-threaded":[16],"parallel":[17],"processing.":[18],"physical":[20],"realized":[23],"by":[24],"the":[25,46,48,54,72,79,86,100,106,110,114,120,123,130,134,141,145],"cache":[27,40,51,70,143],"(TC)":[28],"and":[29,53,74,85,109],"conventional":[31,68],"Multiprocessor-on-a-chip":[35],"(MOC)":[36],"system.":[37],"L1":[39],"CPU":[43,95],"consists":[44],"of":[45,93,122],"TC,":[47,124],"General":[49],"variable":[50],"(GVC)":[52],"instruction":[55,107],"cache.":[56],"IYA":[58,101],"(IY":[59],"architecture)":[60],"that":[61,140],"new":[64],"architecture":[65],"divides":[66],"data":[69],"into":[71],"TC":[73,77],"GVC.":[75],"caches":[78,88],"shared":[80],"variables":[81],"synchronization,":[84],"GVC":[87],"other":[89],"general":[90],"variables.":[91],"Regardless":[92],"core,":[96],"MOC":[98],"can":[102],"utilize":[103],"parallelisms":[104],"from":[105],"level":[108,112,116],"statement":[111],"thread":[115],"systematically.":[117],"To":[118],"estimate":[119],"effect":[121],"preliminary":[125],"experiments":[126],"are":[127],"performed":[128],"on":[129],"multi-chip":[131],"multiprocessor":[132],"including":[133],"stand-alone":[135],"TSVM.":[136],"result":[138],"shows":[139],"improves":[144],"performance.":[146]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
