{"id":"https://openalex.org/W2094087837","doi":"https://doi.org/10.1109/icnc.2014.6975831","title":"NORA circuit design using neuron-MOS transistors","display_name":"NORA circuit design using neuron-MOS transistors","publication_year":2014,"publication_date":"2014-08-01","ids":{"openalex":"https://openalex.org/W2094087837","doi":"https://doi.org/10.1109/icnc.2014.6975831","mag":"2094087837"},"language":"en","primary_location":{"id":"doi:10.1109/icnc.2014.6975831","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icnc.2014.6975831","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 10th International Conference on Natural Computation (ICNC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5012868072","display_name":"Guoqiang Hang","orcid":null},"institutions":[{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Guoqiang Hang","raw_affiliation_strings":["National Mobile Communications Research Laboratory, Southeast University, Nanjing, CHINA","School of Information and Electrical Engineering, Zhejiang University City College, Hangzhou, CHINA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Mobile Communications Research Laboratory, Southeast University, Nanjing, CHINA","institution_ids":[]},{"raw_affiliation_string":"School of Information and Electrical Engineering, Zhejiang University City College, Hangzhou, CHINA","institution_ids":["https://openalex.org/I76130692"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100955382","display_name":"Xuanchang Zhou","orcid":null},"institutions":[{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xuanchang Zhou","raw_affiliation_strings":["School of Information and Electrical Engineering, Zhejiang University City College, Hangzhou, CHINA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Information and Electrical Engineering, Zhejiang University City College, Hangzhou, CHINA","institution_ids":["https://openalex.org/I76130692"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108063871","display_name":"Yang Yang","orcid":"https://orcid.org/0000-0002-3362-7155"},"institutions":[{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yang Yang","raw_affiliation_strings":["School of Information and Electrical Engineering, Zhejiang University City College, Hangzhou, CHINA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Information and Electrical Engineering, Zhejiang University City College, Hangzhou, CHINA","institution_ids":["https://openalex.org/I76130692"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5074822565","display_name":"Danyan Zhang","orcid":"https://orcid.org/0000-0002-0233-494X"},"institutions":[{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Danyan Zhang","raw_affiliation_strings":["School of Information and Electrical Engineering, Zhejiang University City College, Hangzhou, CHINA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Information and Electrical Engineering, Zhejiang University City College, Hangzhou, CHINA","institution_ids":["https://openalex.org/I76130692"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I76130692"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.1303239,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"39","issue":null,"first_page":"181","last_page":"185"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/pmos-logic","display_name":"PMOS logic","score":0.8461726903915405},{"id":"https://openalex.org/keywords/nmos-logic","display_name":"NMOS logic","score":0.8182646036148071},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5995876789093018},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5867700576782227},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.5734183192253113},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.5718424916267395},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5653388500213623},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5452582836151123},{"id":"https://openalex.org/keywords/logic-block","display_name":"Logic block","score":0.5173501372337341},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5047732591629028},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.4755822420120239},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.413545161485672},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.4109700322151184},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.36012548208236694},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.29760491847991943},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22248345613479614},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.18985620141029358},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.1831570267677307},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.12179186940193176}],"concepts":[{"id":"https://openalex.org/C27050352","wikidata":"https://www.wikidata.org/wiki/Q173605","display_name":"PMOS logic","level":4,"score":0.8461726903915405},{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.8182646036148071},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5995876789093018},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5867700576782227},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.5734183192253113},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.5718424916267395},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5653388500213623},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5452582836151123},{"id":"https://openalex.org/C2778325283","wikidata":"https://www.wikidata.org/wiki/Q1125244","display_name":"Logic block","level":3,"score":0.5173501372337341},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5047732591629028},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.4755822420120239},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.413545161485672},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.4109700322151184},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.36012548208236694},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.29760491847991943},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22248345613479614},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.18985620141029358},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.1831570267677307},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.12179186940193176},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icnc.2014.6975831","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icnc.2014.6975831","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 10th International Conference on Natural Computation (ICNC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8899999856948853,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1801025350","https://openalex.org/W2016376185","https://openalex.org/W2025767067","https://openalex.org/W2041121964","https://openalex.org/W2077841234","https://openalex.org/W2108971405","https://openalex.org/W2130173786","https://openalex.org/W2138134203","https://openalex.org/W2158713778","https://openalex.org/W2160142098","https://openalex.org/W2351341406","https://openalex.org/W2538802758","https://openalex.org/W2975643167","https://openalex.org/W6728552157","https://openalex.org/W6981027285","https://openalex.org/W7027842475"],"related_works":["https://openalex.org/W4386261925","https://openalex.org/W2048420745","https://openalex.org/W2082944690","https://openalex.org/W2263373136","https://openalex.org/W2478796561","https://openalex.org/W91469557","https://openalex.org/W4245780952","https://openalex.org/W2168324060","https://openalex.org/W1593362825","https://openalex.org/W2979116331"],"abstract_inverted_index":{"A":[0,55],"No":[1],"Race":[2],"(NORA)":[3],"dynamic":[4,34],"logic":[5,24,28,35,43,63],"using":[6,15,74],"neuron-MOS":[7,18,53,62],"transistor":[8,19],"is":[9,13,69],"presented.":[10],"The":[11,37],"circuit":[12,47],"designed":[14],"the":[16,22,31,42,60,87,90,97,101,105,112],"n-channel":[17,61],"instead":[20],"of":[21,45,59,89,104],"nMOS":[23],"block":[25,29,44,64],"or":[26],"pMOS":[27],"in":[30],"conventional":[32],"NORA":[33,46,93,107],"circuit.":[36],"proposed":[38,91,106],"full-adder":[39],"shows":[40],"that":[41],"can":[48],"be":[49],"simplified":[50],"by":[51,65],"utilizing":[52],"transistor.":[54],"simple":[56],"synthesis":[57],"technique":[58],"employing":[66],"summation":[67],"signal":[68],"discussed.":[70],"HSPICE":[71],"simulation":[72],"results":[73],"TSMC":[75],"0.35\u03bcm":[76],"2-ploy":[77],"4-metal":[78],"CMOS":[79],"process":[80],"with":[81],"1.5V":[82],"power":[83,98],"supply,":[84],"have":[85],"verified":[86],"effectiveness":[88],"neuron-MOS-based":[92],"circuits.":[94],"For":[95],"comparison,":[96],"consumption":[99],"and":[100],"output":[102],"delay":[103],"adders":[108],"are":[109],"measured":[110],"during":[111],"simulations.":[113]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2018,"cited_by_count":1}],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}
