{"id":"https://openalex.org/W2103373038","doi":"https://doi.org/10.1109/icme.2005.1521401","title":"A High-Performance Memory-Efficient Architecture of the Bit-Plane Coder in JPEG 2000","display_name":"A High-Performance Memory-Efficient Architecture of the Bit-Plane Coder in JPEG 2000","publication_year":2005,"publication_date":"2005-10-24","ids":{"openalex":"https://openalex.org/W2103373038","doi":"https://doi.org/10.1109/icme.2005.1521401","mag":"2103373038"},"language":"en","primary_location":{"id":"doi:10.1109/icme.2005.1521401","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icme.2005.1521401","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 IEEE International Conference on Multimedia and Expo","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5067655598","display_name":"Grzegorz Pastuszak","orcid":"https://orcid.org/0000-0002-7368-0495"},"institutions":[{"id":"https://openalex.org/I108403487","display_name":"Warsaw University of Technology","ror":"https://ror.org/00y0xnp53","country_code":"PL","type":"education","lineage":["https://openalex.org/I108403487"]}],"countries":["PL"],"is_corresponding":true,"raw_author_name":"G. Pastuszak","raw_affiliation_strings":["Institute of Radioelectronics, Warsaw University of Technology, Poland","Inst. of Radioelectron., Warsaw Univ. of Technol.#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Radioelectronics, Warsaw University of Technology, Poland","institution_ids":["https://openalex.org/I108403487"]},{"raw_affiliation_string":"Inst. of Radioelectron., Warsaw Univ. of Technol.#TAB#","institution_ids":["https://openalex.org/I108403487"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5067655598"],"corresponding_institution_ids":["https://openalex.org/I108403487"],"apc_list":null,"apc_paid":null,"fwci":0.2565,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.48806683,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"2","issue":null,"first_page":"225","last_page":"228"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10901","display_name":"Advanced Data Compression Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10901","display_name":"Advanced Data Compression Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9962000250816345,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11233","display_name":"Advanced Adaptive Filtering Techniques","score":0.9864000082015991,"subfield":{"id":"https://openalex.org/subfields/2206","display_name":"Computational Mechanics"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7403474450111389},{"id":"https://openalex.org/keywords/stratix","display_name":"Stratix","score":0.6099038124084473},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5969162583351135},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.5915327072143555},{"id":"https://openalex.org/keywords/jpeg-2000","display_name":"JPEG 2000","score":0.4983532428741455},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.459644079208374},{"id":"https://openalex.org/keywords/encoder","display_name":"Encoder","score":0.4429722726345062},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.4333755373954773},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4273064136505127},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.41164064407348633},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.37178903818130493},{"id":"https://openalex.org/keywords/image-compression","display_name":"Image compression","score":0.14946261048316956},{"id":"https://openalex.org/keywords/image-processing","display_name":"Image processing","score":0.08837750554084778}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7403474450111389},{"id":"https://openalex.org/C2776277307","wikidata":"https://www.wikidata.org/wiki/Q22074755","display_name":"Stratix","level":3,"score":0.6099038124084473},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5969162583351135},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.5915327072143555},{"id":"https://openalex.org/C69216139","wikidata":"https://www.wikidata.org/wiki/Q931783","display_name":"JPEG 2000","level":5,"score":0.4983532428741455},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.459644079208374},{"id":"https://openalex.org/C118505674","wikidata":"https://www.wikidata.org/wiki/Q42586063","display_name":"Encoder","level":2,"score":0.4429722726345062},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.4333755373954773},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4273064136505127},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.41164064407348633},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.37178903818130493},{"id":"https://openalex.org/C13481523","wikidata":"https://www.wikidata.org/wiki/Q412438","display_name":"Image compression","level":4,"score":0.14946261048316956},{"id":"https://openalex.org/C9417928","wikidata":"https://www.wikidata.org/wiki/Q1070689","display_name":"Image processing","level":3,"score":0.08837750554084778},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icme.2005.1521401","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icme.2005.1521401","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 IEEE International Conference on Multimedia and Expo","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.5099999904632568}],"awards":[],"funders":[{"id":"https://openalex.org/F4320320300","display_name":"European Commission","ror":"https://ror.org/00k4n6c32"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1581055665","https://openalex.org/W1904135398","https://openalex.org/W2108419324","https://openalex.org/W2111200065","https://openalex.org/W2167120242","https://openalex.org/W4302366751"],"related_works":["https://openalex.org/W1509155667","https://openalex.org/W2518118925","https://openalex.org/W1485756991","https://openalex.org/W2376218453","https://openalex.org/W2031155269","https://openalex.org/W2364622490","https://openalex.org/W2984236338","https://openalex.org/W3208151864","https://openalex.org/W1564576805","https://openalex.org/W4254372399"],"abstract_inverted_index":{"The":[0,19,50],"paper":[1],"presents":[2],"a":[3,22],"high-performance":[4],"architecture":[5,20],"of":[6,47,83],"the":[7,11,72,81],"bit-plane":[8],"coder":[9],"for":[10,59,68],"embedded":[12],"block":[13],"coding":[14],"algorithm":[15],"in":[16,55],"JPEG":[17],"2000.":[18],"adopts":[21],"pipeline":[23],"structure":[24],"and":[25,57,61],"is":[26,53],"dedicated":[27],"to":[28],"generate":[29],"two":[30],"context-symbol":[31],"pairs":[32],"per":[33],"clock":[34],"cycle.":[35],"A":[36],"novel":[37],"method":[38],"called":[39],"dynamic":[40],"significance":[41],"state":[42],"restoring":[43],"(DSSR)":[44],"allows":[45],"reduction":[46],"on-chip":[48],"memories.":[49],"overall":[51],"design":[52],"described":[54],"VHDL":[56],"synthesized":[58],"FPGA":[60,69],"ASIC":[62],"technologies.":[63],"Simulation":[64],"results":[65],"show":[66],"that":[67],"Stratix":[70],"devices,":[71],"engine":[73],"can":[74],"process":[75],"about":[76],"22":[77],"million":[78],"samples":[79],"at":[80],"frequency":[82],"66":[84],"MHz":[85]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
