{"id":"https://openalex.org/W3011606802","doi":"https://doi.org/10.1109/icm48031.2019.9021928","title":"A Novel Current-Domain DRAM Readout Scheme","display_name":"A Novel Current-Domain DRAM Readout Scheme","publication_year":2019,"publication_date":"2019-12-01","ids":{"openalex":"https://openalex.org/W3011606802","doi":"https://doi.org/10.1109/icm48031.2019.9021928","mag":"3011606802"},"language":"en","primary_location":{"id":"doi:10.1109/icm48031.2019.9021928","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icm48031.2019.9021928","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 31st International Conference on Microelectronics (ICM)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5047023966","display_name":"Sherif M. Sharroush","orcid":"https://orcid.org/0000-0001-7911-2571"},"institutions":[{"id":"https://openalex.org/I88017793","display_name":"Port Said University","ror":"https://ror.org/01vx5yq44","country_code":"EG","type":"education","lineage":["https://openalex.org/I88017793"]}],"countries":["EG"],"is_corresponding":true,"raw_author_name":"Sherif M. Sharroush","raw_affiliation_strings":["Department of Electrical Engineering, Faculty of Engineering, Port Said University, Port Said, Egypt"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Faculty of Engineering, Port Said University, Port Said, Egypt","institution_ids":["https://openalex.org/I88017793"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5047023966"],"corresponding_institution_ids":["https://openalex.org/I88017793"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.17620291,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"249","last_page":"252"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9970999956130981,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.9406218528747559},{"id":"https://openalex.org/keywords/dynamic-random-access-memory","display_name":"Dynamic random-access memory","score":0.755632221698761},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.6500338912010193},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6336057782173157},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.6282029151916504},{"id":"https://openalex.org/keywords/access-time","display_name":"Access time","score":0.6190818548202515},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6136252880096436},{"id":"https://openalex.org/keywords/random-access","display_name":"Random access","score":0.6062382459640503},{"id":"https://openalex.org/keywords/capacitance","display_name":"Capacitance","score":0.5676417350769043},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.5634377598762512},{"id":"https://openalex.org/keywords/random-access-memory","display_name":"Random access memory","score":0.559277355670929},{"id":"https://openalex.org/keywords/memory-cell","display_name":"Memory cell","score":0.5317754745483398},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5116289258003235},{"id":"https://openalex.org/keywords/domain","display_name":"Domain (mathematical analysis)","score":0.4764305055141449},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.42847999930381775},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.3527962565422058},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.31764018535614014},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.3132488429546356},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20988783240318298},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.17312172055244446},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.1388220191001892},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.08515843749046326},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.07680433988571167}],"concepts":[{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.9406218528747559},{"id":"https://openalex.org/C118702147","wikidata":"https://www.wikidata.org/wiki/Q189396","display_name":"Dynamic random-access memory","level":3,"score":0.755632221698761},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.6500338912010193},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6336057782173157},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.6282029151916504},{"id":"https://openalex.org/C194080101","wikidata":"https://www.wikidata.org/wiki/Q46306","display_name":"Access time","level":2,"score":0.6190818548202515},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6136252880096436},{"id":"https://openalex.org/C101722063","wikidata":"https://www.wikidata.org/wiki/Q218825","display_name":"Random access","level":2,"score":0.6062382459640503},{"id":"https://openalex.org/C30066665","wikidata":"https://www.wikidata.org/wiki/Q164399","display_name":"Capacitance","level":3,"score":0.5676417350769043},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.5634377598762512},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.559277355670929},{"id":"https://openalex.org/C2776638159","wikidata":"https://www.wikidata.org/wiki/Q18343761","display_name":"Memory cell","level":4,"score":0.5317754745483398},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5116289258003235},{"id":"https://openalex.org/C36503486","wikidata":"https://www.wikidata.org/wiki/Q11235244","display_name":"Domain (mathematical analysis)","level":2,"score":0.4764305055141449},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.42847999930381775},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.3527962565422058},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.31764018535614014},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.3132488429546356},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20988783240318298},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.17312172055244446},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.1388220191001892},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.08515843749046326},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.07680433988571167},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C17525397","wikidata":"https://www.wikidata.org/wiki/Q176140","display_name":"Electrode","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icm48031.2019.9021928","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icm48031.2019.9021928","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 31st International Conference on Microelectronics (ICM)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.550000011920929,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1955819279","https://openalex.org/W2050182297","https://openalex.org/W2112553085","https://openalex.org/W2507016108","https://openalex.org/W2557781131","https://openalex.org/W2810550170","https://openalex.org/W4210947991"],"related_works":["https://openalex.org/W2142797216","https://openalex.org/W2119817814","https://openalex.org/W2098352042","https://openalex.org/W1928025959","https://openalex.org/W3139525557","https://openalex.org/W4232117715","https://openalex.org/W2171636992","https://openalex.org/W2065778483","https://openalex.org/W2145302308","https://openalex.org/W2186356227"],"abstract_inverted_index":{"The":[0,26,70,86],"one-transistor":[1],"one-capacitor":[2],"(1T":[3],"-1C)":[4],"memory":[5],"cell":[6],"is":[7,35,64,73,90],"considered":[8],"the":[9,36,43,48,54,67,78,96],"industry":[10],"standard":[11],"in":[12,66],"dynamic":[13],"random-access":[14],"memories":[15,34],"(DRAMs)":[16],"due":[17,41],"to":[18,42,45],"its":[19],"low":[20],"cost":[21],"and":[22],"high":[23],"packing":[24],"density.":[25],"main":[27],"challenge":[28],"associated":[29],"with":[30,47],"this":[31,57],"type":[32],"of":[33,53,95],"relatively":[37,49],"large":[38,50],"read-access":[39,88],"time":[40,89],"need":[44],"deal":[46],"parasitic":[51],"capacitance":[52],"bitline.":[55],"In":[56],"paper,":[58],"a":[59],"novel":[60],"fast":[61],"readout":[62],"scheme":[63,72],"proposed":[65,71],"current":[68],"domain.":[69],"verified":[74],"by":[75],"simulation":[76],"adopting":[77],"45":[79],"nm":[80],"CMOS":[81],"Berkeley":[82],"predictive-technology":[83],"model":[84],"(BPTM).":[85],"average":[87],"30%":[91],"smaller":[92],"than":[93],"that":[94],"conventional":[97],"readout.":[98]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
