{"id":"https://openalex.org/W2798282005","doi":"https://doi.org/10.1109/icit.2018.8352429","title":"Supporting temporal and spatial isolation in a hypervisor for ARM multicore platforms","display_name":"Supporting temporal and spatial isolation in a hypervisor for ARM multicore platforms","publication_year":2018,"publication_date":"2018-02-01","ids":{"openalex":"https://openalex.org/W2798282005","doi":"https://doi.org/10.1109/icit.2018.8352429","mag":"2798282005"},"language":"en","primary_location":{"id":"doi:10.1109/icit.2018.8352429","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icit.2018.8352429","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE International Conference on Industrial Technology (ICIT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5019017341","display_name":"Paolo Modica","orcid":null},"institutions":[{"id":"https://openalex.org/I162290304","display_name":"Scuola Superiore Sant'Anna","ror":"https://ror.org/025602r80","country_code":"IT","type":"education","lineage":["https://openalex.org/I162290304"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Paolo Modica","raw_affiliation_strings":["Scuola Superiore Sant'Anna, Pisa, Italy"],"affiliations":[{"raw_affiliation_string":"Scuola Superiore Sant'Anna, Pisa, Italy","institution_ids":["https://openalex.org/I162290304"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5072482410","display_name":"Alessandro Biondi","orcid":"https://orcid.org/0000-0002-6625-9336"},"institutions":[{"id":"https://openalex.org/I162290304","display_name":"Scuola Superiore Sant'Anna","ror":"https://ror.org/025602r80","country_code":"IT","type":"education","lineage":["https://openalex.org/I162290304"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Alessandro Biondi","raw_affiliation_strings":["Scuola Superiore Sant'Anna, Pisa, Italy"],"affiliations":[{"raw_affiliation_string":"Scuola Superiore Sant'Anna, Pisa, Italy","institution_ids":["https://openalex.org/I162290304"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5024920325","display_name":"Giorgio Buttazzo","orcid":"https://orcid.org/0000-0003-4959-4017"},"institutions":[{"id":"https://openalex.org/I162290304","display_name":"Scuola Superiore Sant'Anna","ror":"https://ror.org/025602r80","country_code":"IT","type":"education","lineage":["https://openalex.org/I162290304"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Giorgio Buttazzo","raw_affiliation_strings":["Scuola Superiore Sant'Anna, Pisa, Italy"],"affiliations":[{"raw_affiliation_string":"Scuola Superiore Sant'Anna, Pisa, Italy","institution_ids":["https://openalex.org/I162290304"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5088885271","display_name":"Anup Patel","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Anup Patel","raw_affiliation_strings":["Bangalore, India"],"affiliations":[{"raw_affiliation_string":"Bangalore, India","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5019017341"],"corresponding_institution_ids":["https://openalex.org/I162290304"],"apc_list":null,"apc_paid":null,"fwci":3.6849,"has_fulltext":false,"cited_by_count":41,"citation_normalized_percentile":{"value":0.93633089,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":94,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1651","last_page":"1657"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/hypervisor","display_name":"Hypervisor","score":0.8954185247421265},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8227647542953491},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.7371736764907837},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.6534068584442139},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5974388122558594},{"id":"https://openalex.org/keywords/virtualization","display_name":"Virtualization","score":0.5813798904418945},{"id":"https://openalex.org/keywords/temporal-isolation-among-virtual-machines","display_name":"Temporal isolation among virtual machines","score":0.4791126251220703},{"id":"https://openalex.org/keywords/isolation","display_name":"Isolation (microbiology)","score":0.4737083613872528},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.4703875780105591},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.42998045682907104},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.4121532440185547},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2417309284210205},{"id":"https://openalex.org/keywords/cloud-computing","display_name":"Cloud computing","score":0.1426820456981659}],"concepts":[{"id":"https://openalex.org/C112904061","wikidata":"https://www.wikidata.org/wiki/Q1077480","display_name":"Hypervisor","level":4,"score":0.8954185247421265},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8227647542953491},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.7371736764907837},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.6534068584442139},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5974388122558594},{"id":"https://openalex.org/C513985346","wikidata":"https://www.wikidata.org/wiki/Q270471","display_name":"Virtualization","level":3,"score":0.5813798904418945},{"id":"https://openalex.org/C142355369","wikidata":"https://www.wikidata.org/wiki/Q7698919","display_name":"Temporal isolation among virtual machines","level":4,"score":0.4791126251220703},{"id":"https://openalex.org/C2775941552","wikidata":"https://www.wikidata.org/wiki/Q25212305","display_name":"Isolation (microbiology)","level":2,"score":0.4737083613872528},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.4703875780105591},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.42998045682907104},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.4121532440185547},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2417309284210205},{"id":"https://openalex.org/C79974875","wikidata":"https://www.wikidata.org/wiki/Q483639","display_name":"Cloud computing","level":2,"score":0.1426820456981659},{"id":"https://openalex.org/C89423630","wikidata":"https://www.wikidata.org/wiki/Q7193","display_name":"Microbiology","level":1,"score":0.0},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/icit.2018.8352429","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icit.2018.8352429","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE International Conference on Industrial Technology (ICIT)","raw_type":"proceedings-article"},{"id":"pmh:oai:www.iris.sssup.it:11382/527029","is_oa":false,"landing_page_url":"http://hdl.handle.net/11382/527029","pdf_url":null,"source":{"id":"https://openalex.org/S4377196376","display_name":"CINECA IRIS Institutional Research Information System (Sant'Anna School of Advanced Studies)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I162290304","host_organization_name":"Scuola Superiore Sant'Anna","host_organization_lineage":["https://openalex.org/I162290304"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.44999998807907104,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1963479629","https://openalex.org/W2015827499","https://openalex.org/W2114620069","https://openalex.org/W2115078506","https://openalex.org/W2149075075","https://openalex.org/W2230430964","https://openalex.org/W2344136895","https://openalex.org/W2464364540","https://openalex.org/W2531496768","https://openalex.org/W2569747718","https://openalex.org/W2614629969","https://openalex.org/W6682152478"],"related_works":["https://openalex.org/W2211851094","https://openalex.org/W2120735849","https://openalex.org/W2373469112","https://openalex.org/W2957116650","https://openalex.org/W2112715807","https://openalex.org/W2811048697","https://openalex.org/W1982715569","https://openalex.org/W2032031011","https://openalex.org/W3009835977","https://openalex.org/W2144642151"],"abstract_inverted_index":{"This":[0],"paper":[1],"addresses":[2],"the":[3,29,39,44,53,65,73,89,97,112,130,134,144,151,154],"problem":[4],"of":[5,35,67,80,133,153,161],"providing":[6],"spatial":[7],"and":[8,43,52],"temporal":[9],"isolation":[10,110],"between":[11],"execution":[12],"domains":[13,164],"in":[14],"a":[15,103,120,158],"hypervisor":[16,51],"running":[17,165],"on":[18,72,111,143,157],"an":[19],"ARM":[20,54,90],"multicore":[21,37],"platform.":[22],"Isolation":[23],"is":[24],"achieved":[25],"by":[26,78,102,118],"carefully":[27],"managing":[28],"two":[30],"primary":[31],"shared":[32],"hardware":[33],"resources":[34],"today's":[36],"platforms:":[38],"last-level":[40],"cache":[41,81],"(LLC)":[42],"DRAM":[45,113],"memory":[46,98,105,121],"controller.":[47],"The":[48],"XVISOR":[49],"open-source":[50],"Cortex":[55],"A7":[56],"platform":[57],"have":[58],"been":[59,76,85,116,127,141],"used":[60],"as":[61],"reference":[62],"systems":[63],"for":[64],"purpose":[66],"this":[68],"work.":[69],"Spatial":[70],"partitioning":[71],"LLC":[74],"has":[75,84,115,126,140],"implemented":[77,117,155],"means":[79],"coloring,":[82],"which":[83,125],"tightly":[86],"integrated":[87],"with":[88,96,129],"virtualization":[91,99],"extensions":[92],"(ARM-VE)":[93],"to":[94],"deal":[95],"capabilities":[100],"offered":[101],"two-stage":[104],"management":[106],"unit":[107],"(MMU).":[108],"Temporal":[109],"controller":[114],"realizing":[119],"bandwidth":[122],"reservation":[123],"mechanism,":[124],"combined":[128],"scheduling":[131],"logic":[132],"hypervisor.":[135],"An":[136],"extensive":[137],"experimental":[138],"evaluation":[139],"performed":[142],"popular":[145],"Raspberry":[146],"Pi":[147],"2":[148],"board,":[149],"showing":[150],"effectiveness":[152],"solutions":[156],"case-study":[159],"composed":[160],"multiple":[162],"Linux":[163],"state-of-the-art":[166],"benchmarks.":[167]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":5},{"year":2024,"cited_by_count":7},{"year":2023,"cited_by_count":9},{"year":2022,"cited_by_count":5},{"year":2021,"cited_by_count":5},{"year":2020,"cited_by_count":4},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":2}],"updated_date":"2026-03-26T06:05:38.182114","created_date":"2025-10-10T00:00:00"}