{"id":"https://openalex.org/W2513392679","doi":"https://doi.org/10.1109/icis.2016.7550744","title":"A cache memory with unit tile and line accessibility","display_name":"A cache memory with unit tile and line accessibility","publication_year":2016,"publication_date":"2016-06-01","ids":{"openalex":"https://openalex.org/W2513392679","doi":"https://doi.org/10.1109/icis.2016.7550744","mag":"2513392679"},"language":"en","primary_location":{"id":"doi:10.1109/icis.2016.7550744","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icis.2016.7550744","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE/ACIS 15th International Conference on Computer and Information Science (ICIS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5058373828","display_name":"Baokang Wang","orcid":"https://orcid.org/0000-0002-5709-7056"},"institutions":[{"id":"https://openalex.org/I178574317","display_name":"Mie University","ror":"https://ror.org/01529vy56","country_code":"JP","type":"education","lineage":["https://openalex.org/I178574317"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"BaoKang Wang","raw_affiliation_strings":["Graduate School of Engineering, Mie University Japan"],"affiliations":[{"raw_affiliation_string":"Graduate School of Engineering, Mie University Japan","institution_ids":["https://openalex.org/I178574317"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112415279","display_name":"Yuki Fukazawa","orcid":null},"institutions":[{"id":"https://openalex.org/I178574317","display_name":"Mie University","ror":"https://ror.org/01529vy56","country_code":"JP","type":"education","lineage":["https://openalex.org/I178574317"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Yuki Fukazawa","raw_affiliation_strings":["Graduate School of Engineering, Mie University Japan"],"affiliations":[{"raw_affiliation_string":"Graduate School of Engineering, Mie University Japan","institution_ids":["https://openalex.org/I178574317"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102345053","display_name":"Toshio Kondo","orcid":null},"institutions":[{"id":"https://openalex.org/I178574317","display_name":"Mie University","ror":"https://ror.org/01529vy56","country_code":"JP","type":"education","lineage":["https://openalex.org/I178574317"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Toshio Kondo","raw_affiliation_strings":["Graduate School of Engineering, Mie University Japan"],"affiliations":[{"raw_affiliation_string":"Graduate School of Engineering, Mie University Japan","institution_ids":["https://openalex.org/I178574317"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5104110650","display_name":"Takahiro Sasaki","orcid":null},"institutions":[{"id":"https://openalex.org/I178574317","display_name":"Mie University","ror":"https://ror.org/01529vy56","country_code":"JP","type":"education","lineage":["https://openalex.org/I178574317"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Takahiro Sasaki","raw_affiliation_strings":["Graduate School of Engineering, Mie University Japan"],"affiliations":[{"raw_affiliation_string":"Graduate School of Engineering, Mie University Japan","institution_ids":["https://openalex.org/I178574317"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5058373828"],"corresponding_institution_ids":["https://openalex.org/I178574317"],"apc_list":null,"apc_paid":null,"fwci":0.946,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.73829227,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8057512044906616},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.7653308510780334},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.7307026982307434},{"id":"https://openalex.org/keywords/page-cache","display_name":"Page cache","score":0.6394137740135193},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.5611821413040161},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.5329813361167908},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.47809717059135437},{"id":"https://openalex.org/keywords/cache-pollution","display_name":"Cache pollution","score":0.45683544874191284},{"id":"https://openalex.org/keywords/access-time","display_name":"Access time","score":0.43276605010032654},{"id":"https://openalex.org/keywords/cache-oblivious-algorithm","display_name":"Cache-oblivious algorithm","score":0.4123649299144745},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.38316604495048523}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8057512044906616},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.7653308510780334},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.7307026982307434},{"id":"https://openalex.org/C36340418","wikidata":"https://www.wikidata.org/wiki/Q7124288","display_name":"Page cache","level":5,"score":0.6394137740135193},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.5611821413040161},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.5329813361167908},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.47809717059135437},{"id":"https://openalex.org/C113166858","wikidata":"https://www.wikidata.org/wiki/Q5015981","display_name":"Cache pollution","level":5,"score":0.45683544874191284},{"id":"https://openalex.org/C194080101","wikidata":"https://www.wikidata.org/wiki/Q46306","display_name":"Access time","level":2,"score":0.43276605010032654},{"id":"https://openalex.org/C59687516","wikidata":"https://www.wikidata.org/wiki/Q5015938","display_name":"Cache-oblivious algorithm","level":5,"score":0.4123649299144745},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.38316604495048523}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icis.2016.7550744","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icis.2016.7550744","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE/ACIS 15th International Conference on Computer and Information Science (ICIS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320322832","display_name":"University of Tokyo","ror":"https://ror.org/057zh3y96"},{"id":"https://openalex.org/F4320334764","display_name":"Japan Society for the Promotion of Science","ror":"https://ror.org/00hhkn466"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W99288580","https://openalex.org/W1510658361","https://openalex.org/W1992678651","https://openalex.org/W2019618182","https://openalex.org/W2061291998","https://openalex.org/W2073436418","https://openalex.org/W2098220211","https://openalex.org/W2109222446","https://openalex.org/W2113420676","https://openalex.org/W2142599225","https://openalex.org/W2158158791","https://openalex.org/W2171877898","https://openalex.org/W3105613233","https://openalex.org/W4245312332","https://openalex.org/W4253068647","https://openalex.org/W4285719527","https://openalex.org/W6604058846","https://openalex.org/W6685158276"],"related_works":["https://openalex.org/W2098406302","https://openalex.org/W2535115842","https://openalex.org/W2121191383","https://openalex.org/W1584415117","https://openalex.org/W2116323004","https://openalex.org/W2020176098","https://openalex.org/W2546991807","https://openalex.org/W2734782074","https://openalex.org/W4252570104","https://openalex.org/W2116334158"],"abstract_inverted_index":{"Ineffective":[0],"data":[1,12,73,98,123,159],"access":[2,50,72,94,99],"of":[3,65,151,190,197],"cache":[4,28,70,90,124,154,195],"memories":[5],"becomes":[6],"a":[7,27,57,157],"bottleneck":[8],"for":[9],"efficient":[10],"2-dimensional(2-D)":[11],"processing":[13,17],"such":[14],"as":[15,193],"image":[16],"and":[18,34,88,121,132,140,181],"matrix":[19,138,146],"multiplication.":[20],"In":[21],"order":[22,49,131,135],"to":[23,51,96,186],"solve":[24],"this":[25,52],"problem,":[26],"memory":[29,196],"with":[30,127,156],"both":[31,118],"unit":[32,35],"tile":[33,93],"line":[36],"accessibility,":[37],"based":[38],"on":[39],"4-level":[40,84,113],"Z-order":[41,85,114],"tiling":[42,86,115],"layout":[43,53,87,116,136],"is":[44,54],"proposed.":[45],"Conventional":[46],"raster":[47,129],"scan":[48,130],"enabled":[55],"by":[56,83,171],"hardware-base":[58],"address":[59,66],"translation,":[60],"which":[61],"can":[62,71,104],"eliminate":[63],"overhead":[64],"calculation.":[67],"The":[68],"proposed":[69,153],"in":[74,76,100,137,163],"parallel":[75,97],"vertical(unit":[77],"tile)":[78],"or":[79,200],"horizontal(unit":[80],"line)":[81],"direction":[82,103],"multi-bank":[89],"organization.":[91],"Unit":[92],"corresponding":[95],"the":[101,112,128,133,152,191],"vertical":[102],"exploit":[105],"2-D":[106],"locality.":[107],"Simulation":[108],"results":[109],"show":[110],"that":[111],"provides":[117],"less":[119],"TLB":[120],"L1":[122],"misses":[125],"compared":[126],"Morton":[134],"multiplication":[139],"LU":[141],"decomposition,":[142],"especially":[143],"at":[144],"larger":[145],"size.":[147],"An":[148],"LSI":[149],"chip":[150],"combined":[155],"SIMD-based":[158],"path":[160],"was":[161,184],"designed":[162],"2.5":[164],"\u00d7":[165],"5mm":[166],"<sup":[167],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[168],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[169],"area":[170],"using":[172],"0.18\u03bcm":[173],"CMOS":[174],"technology.":[175],"Under":[176],"3.8ns":[177],"clock":[178,188],"period,":[179],"read":[180],"write":[182],"latency":[183],"suppressed":[185],"3":[187],"cycles":[189],"same":[192],"conventional":[194],"an":[198],"Intel":[199],"ARM":[201],"high-performance":[202],"processor.":[203]},"counts_by_year":[{"year":2019,"cited_by_count":2},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}