{"id":"https://openalex.org/W2165456233","doi":"https://doi.org/10.1109/icis.2014.6912102","title":"Synchronization for QDPSK &amp;#x2014;Costas loop and Gardner algorithm using FPGAs","display_name":"Synchronization for QDPSK &amp;#x2014;Costas loop and Gardner algorithm using FPGAs","publication_year":2014,"publication_date":"2014-06-01","ids":{"openalex":"https://openalex.org/W2165456233","doi":"https://doi.org/10.1109/icis.2014.6912102","mag":"2165456233"},"language":"en","primary_location":{"id":"doi:10.1109/icis.2014.6912102","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icis.2014.6912102","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE/ACIS 13th International Conference on Computer and Information Science (ICIS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101835586","display_name":"Jie Hua","orcid":"https://orcid.org/0000-0002-7721-5240"},"institutions":[{"id":"https://openalex.org/I126520041","display_name":"University of Science and Technology of China","ror":"https://ror.org/04c4dkn09","country_code":"CN","type":"education","lineage":["https://openalex.org/I126520041","https://openalex.org/I19820366"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jie Hua","raw_affiliation_strings":["Key Laboratory of Electromagnetic Space Information, University of Science and Technology of China, Hefei, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Key Laboratory of Electromagnetic Space Information, University of Science and Technology of China, Hefei, China","institution_ids":["https://openalex.org/I126520041"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5044461260","display_name":"Lingyun Zhou","orcid":"https://orcid.org/0000-0002-3219-4896"},"institutions":[{"id":"https://openalex.org/I126520041","display_name":"University of Science and Technology of China","ror":"https://ror.org/04c4dkn09","country_code":"CN","type":"education","lineage":["https://openalex.org/I126520041","https://openalex.org/I19820366"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Lingyun Zhou","raw_affiliation_strings":["Key Laboratory of Electromagnetic Space Information, University of Science and Technology of China, Hefei, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Key Laboratory of Electromagnetic Space Information, University of Science and Technology of China, Hefei, China","institution_ids":["https://openalex.org/I126520041"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100449483","display_name":"Chang Chen","orcid":"https://orcid.org/0000-0002-5378-4107"},"institutions":[{"id":"https://openalex.org/I126520041","display_name":"University of Science and Technology of China","ror":"https://ror.org/04c4dkn09","country_code":"CN","type":"education","lineage":["https://openalex.org/I126520041","https://openalex.org/I19820366"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Chang Chen","raw_affiliation_strings":["Key Laboratory of Electromagnetic Space Information, University of Science and Technology of China, Hefei, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Key Laboratory of Electromagnetic Space Information, University of Science and Technology of China, Hefei, China","institution_ids":["https://openalex.org/I126520041"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101694440","display_name":"Lin Jiang","orcid":"https://orcid.org/0000-0001-8282-1176"},"institutions":[{"id":"https://openalex.org/I126520041","display_name":"University of Science and Technology of China","ror":"https://ror.org/04c4dkn09","country_code":"CN","type":"education","lineage":["https://openalex.org/I126520041","https://openalex.org/I19820366"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Lin Jiang","raw_affiliation_strings":["Key Laboratory of Electromagnetic Space Information, University of Science and Technology of China, Hefei, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Key Laboratory of Electromagnetic Space Information, University of Science and Technology of China, Hefei, China","institution_ids":["https://openalex.org/I126520041"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I126520041"],"apc_list":null,"apc_paid":null,"fwci":1.2237,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.78102855,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"32","issue":null,"first_page":"27","last_page":"31"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9937000274658203,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9937000274658203,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9884999990463257,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10125","display_name":"Advanced Wireless Communication Techniques","score":0.9817000031471252,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/modelsim","display_name":"ModelSim","score":0.9339885711669922},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8465360999107361},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.8329132795333862},{"id":"https://openalex.org/keywords/stratix","display_name":"Stratix","score":0.7929027080535889},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7353882193565369},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.6769749522209167},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4352363646030426},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.40081924200057983},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3386772871017456},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.14609533548355103},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.07797583937644958}],"concepts":[{"id":"https://openalex.org/C2778571676","wikidata":"https://www.wikidata.org/wiki/Q3317826","display_name":"ModelSim","level":4,"score":0.9339885711669922},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8465360999107361},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.8329132795333862},{"id":"https://openalex.org/C2776277307","wikidata":"https://www.wikidata.org/wiki/Q22074755","display_name":"Stratix","level":3,"score":0.7929027080535889},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7353882193565369},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.6769749522209167},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4352363646030426},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.40081924200057983},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3386772871017456},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.14609533548355103},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.07797583937644958},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icis.2014.6912102","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icis.2014.6912102","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE/ACIS 13th International Conference on Computer and Information Science (ICIS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.49000000953674316,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1968612560","https://openalex.org/W1971114551","https://openalex.org/W2099611565","https://openalex.org/W2127691264","https://openalex.org/W2135088353","https://openalex.org/W2549357314","https://openalex.org/W4285719527","https://openalex.org/W6680060271","https://openalex.org/W6697084112","https://openalex.org/W6729136951"],"related_works":["https://openalex.org/W2080235730","https://openalex.org/W2347617805","https://openalex.org/W2389765791","https://openalex.org/W2534868112","https://openalex.org/W2694160303","https://openalex.org/W1509155667","https://openalex.org/W4297665406","https://openalex.org/W3028347934","https://openalex.org/W2377898907","https://openalex.org/W2165456233"],"abstract_inverted_index":{"This":[0],"paper":[1],"discusses":[2],"the":[3,8,28,35,55,74,78,93,97],"mathematical":[4],"model":[5],"and":[6,16,34,57,62,91,100],"implements":[7],"physical":[9],"verification":[10,76],"when":[11,65],"Carrier":[12,60],"synchronization":[13,18,61,64],"(carrier":[14],"loop)":[15],"Timing":[17,63],"(Gardner":[19],"algorithm)":[20],"working":[21],"simultaneously.":[22],"Firstly,":[23],"a":[24,49],"brief":[25],"analysis":[26,51],"of":[27,59,67,88],"above":[29],"mentioned":[30],"systems":[31],"is":[32,38,52],"completed,":[33],"functional":[36],"simulation":[37],"accomplished":[39],"by":[40],"Verilog":[41],"HDL":[42],"code":[43],"on":[44,77],"ModelSim":[45],"platform.":[46],"In":[47],"addition,":[48],"systematic":[50],"done":[53],"for":[54],"workflow":[56],"interrelation":[58],"both":[66],"them":[68],"are":[69],"active.":[70],"Finally,":[71],"we":[72],"implement":[73],"hardware":[75],"Stratix":[79],"series":[80],"field":[81],"programmable":[82],"gate":[83],"array":[84],"(FPGA)":[85],"device":[86],"EP3SL150F1152C2N":[87],"Altera":[89],"Company,":[90],"give":[92],"engineering":[94],"results":[95],"through":[96],"RF":[98],"part":[99],"space":[101],"transmission.":[102]},"counts_by_year":[{"year":2023,"cited_by_count":3},{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
