{"id":"https://openalex.org/W2513067770","doi":"https://doi.org/10.1109/icip.2016.7532742","title":"An efficient sub-sample interpolator hardware for VP9-10 standards","display_name":"An efficient sub-sample interpolator hardware for VP9-10 standards","publication_year":2016,"publication_date":"2016-08-17","ids":{"openalex":"https://openalex.org/W2513067770","doi":"https://doi.org/10.1109/icip.2016.7532742","mag":"2513067770"},"language":"en","primary_location":{"id":"doi:10.1109/icip.2016.7532742","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icip.2016.7532742","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE International Conference on Image Processing (ICIP)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5064318827","display_name":"Guilherme Paim","orcid":"https://orcid.org/0000-0001-7809-9563"},"institutions":[{"id":"https://openalex.org/I169248161","display_name":"Universidade Federal de Pelotas","ror":"https://ror.org/05msy9z54","country_code":"BR","type":"education","lineage":["https://openalex.org/I169248161"]}],"countries":["BR"],"is_corresponding":true,"raw_author_name":"Guilherme Paim","raw_affiliation_strings":["Group of Architectures and Integrated Circuits (GACI), Federal University of Pelot as (UFPel)"],"affiliations":[{"raw_affiliation_string":"Group of Architectures and Integrated Circuits (GACI), Federal University of Pelot as (UFPel)","institution_ids":["https://openalex.org/I169248161"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5050337546","display_name":"Wagner Penny","orcid":"https://orcid.org/0000-0003-2227-1218"},"institutions":[{"id":"https://openalex.org/I169248161","display_name":"Universidade Federal de Pelotas","ror":"https://ror.org/05msy9z54","country_code":"BR","type":"education","lineage":["https://openalex.org/I169248161"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Wagner Penny","raw_affiliation_strings":["Group of Architectures and Integrated Circuits (GACI), Federal University of Pelot as (UFPel)"],"affiliations":[{"raw_affiliation_string":"Group of Architectures and Integrated Circuits (GACI), Federal University of Pelot as (UFPel)","institution_ids":["https://openalex.org/I169248161"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5079262645","display_name":"Jones G\u00f6ebel","orcid":"https://orcid.org/0000-0002-5937-9794"},"institutions":[{"id":"https://openalex.org/I169248161","display_name":"Universidade Federal de Pelotas","ror":"https://ror.org/05msy9z54","country_code":"BR","type":"education","lineage":["https://openalex.org/I169248161"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Jones Goebel","raw_affiliation_strings":["Group of Architectures and Integrated Circuits (GACI), Federal University of Pelot as (UFPel)"],"affiliations":[{"raw_affiliation_string":"Group of Architectures and Integrated Circuits (GACI), Federal University of Pelot as (UFPel)","institution_ids":["https://openalex.org/I169248161"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034889625","display_name":"Vladimir Afonso","orcid":"https://orcid.org/0000-0002-5761-4121"},"institutions":[{"id":"https://openalex.org/I126460647","display_name":"Universidade Federal do Rio Grande","ror":"https://ror.org/05hpfkn88","country_code":"BR","type":"education","lineage":["https://openalex.org/I126460647"]},{"id":"https://openalex.org/I94328231","display_name":"University of Rio Grande and Rio Grande Community College","ror":"https://ror.org/02sghbs34","country_code":"US","type":"education","lineage":["https://openalex.org/I94328231"]},{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR","US"],"is_corresponding":false,"raw_author_name":"Vladimir Afonso","raw_affiliation_strings":["Graduate Program in Microelectronics (PGMicro), Federal University of Rio Grande do SuI (UFRGS)"],"affiliations":[{"raw_affiliation_string":"Graduate Program in Microelectronics (PGMicro), Federal University of Rio Grande do SuI (UFRGS)","institution_ids":["https://openalex.org/I94328231","https://openalex.org/I130442723","https://openalex.org/I126460647"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043190662","display_name":"Altamiro Susin","orcid":"https://orcid.org/0000-0001-7034-5336"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]},{"id":"https://openalex.org/I94328231","display_name":"University of Rio Grande and Rio Grande Community College","ror":"https://ror.org/02sghbs34","country_code":"US","type":"education","lineage":["https://openalex.org/I94328231"]},{"id":"https://openalex.org/I126460647","display_name":"Universidade Federal do Rio Grande","ror":"https://ror.org/05hpfkn88","country_code":"BR","type":"education","lineage":["https://openalex.org/I126460647"]}],"countries":["BR","US"],"is_corresponding":false,"raw_author_name":"Altamiro Susin","raw_affiliation_strings":["Graduate Program in Microelectronics (PGMicro), Federal University of Rio Grande do SuI (UFRGS)"],"affiliations":[{"raw_affiliation_string":"Graduate Program in Microelectronics (PGMicro), Federal University of Rio Grande do SuI (UFRGS)","institution_ids":["https://openalex.org/I94328231","https://openalex.org/I130442723","https://openalex.org/I126460647"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081630912","display_name":"Marcelo Porto","orcid":"https://orcid.org/0000-0003-3827-3023"},"institutions":[{"id":"https://openalex.org/I169248161","display_name":"Universidade Federal de Pelotas","ror":"https://ror.org/05msy9z54","country_code":"BR","type":"education","lineage":["https://openalex.org/I169248161"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Marcelo Porto","raw_affiliation_strings":["Group of Architectures and Integrated Circuits (GACI), Federal University of Pelot as (UFPel)"],"affiliations":[{"raw_affiliation_string":"Group of Architectures and Integrated Circuits (GACI), Federal University of Pelot as (UFPel)","institution_ids":["https://openalex.org/I169248161"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5057414253","display_name":"Bruno Zatt","orcid":"https://orcid.org/0000-0002-8045-957X"},"institutions":[{"id":"https://openalex.org/I169248161","display_name":"Universidade Federal de Pelotas","ror":"https://ror.org/05msy9z54","country_code":"BR","type":"education","lineage":["https://openalex.org/I169248161"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Bruno Zatt","raw_affiliation_strings":["Group of Architectures and Integrated Circuits (GACI), Federal University of Pelot as (UFPel)"],"affiliations":[{"raw_affiliation_string":"Group of Architectures and Integrated Circuits (GACI), Federal University of Pelot as (UFPel)","institution_ids":["https://openalex.org/I169248161"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5070735330","display_name":"Luciano Agostini","orcid":"https://orcid.org/0000-0002-3421-5830"},"institutions":[{"id":"https://openalex.org/I169248161","display_name":"Universidade Federal de Pelotas","ror":"https://ror.org/05msy9z54","country_code":"BR","type":"education","lineage":["https://openalex.org/I169248161"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Luciano Agostini","raw_affiliation_strings":["Group of Architectures and Integrated Circuits (GACI), Federal University of Pelot as (UFPel)"],"affiliations":[{"raw_affiliation_string":"Group of Architectures and Integrated Circuits (GACI), Federal University of Pelot as (UFPel)","institution_ids":["https://openalex.org/I169248161"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":8,"corresponding_author_ids":["https://openalex.org/A5064318827"],"corresponding_institution_ids":["https://openalex.org/I169248161"],"apc_list":null,"apc_paid":null,"fwci":0.7769,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.7201463,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"2167","last_page":"2171"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10741","display_name":"Video Coding and Compression Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10741","display_name":"Video Coding and Compression Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10531","display_name":"Advanced Vision and Imaging","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.6516945362091064},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.6341544389724731},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6322118639945984},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.6290514469146729},{"id":"https://openalex.org/keywords/motion-compensation","display_name":"Motion compensation","score":0.5304999351501465},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.4508129060268402},{"id":"https://openalex.org/keywords/hardware-architecture","display_name":"Hardware architecture","score":0.4460398852825165},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.43805521726608276},{"id":"https://openalex.org/keywords/coding","display_name":"Coding (social sciences)","score":0.42897307872772217},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4243430495262146},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.20662176609039307},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20414286851882935},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.16805365681648254},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.12894970178604126},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.07947805523872375}],"concepts":[{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.6516945362091064},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.6341544389724731},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6322118639945984},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.6290514469146729},{"id":"https://openalex.org/C128840427","wikidata":"https://www.wikidata.org/wiki/Q1302174","display_name":"Motion compensation","level":2,"score":0.5304999351501465},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.4508129060268402},{"id":"https://openalex.org/C65232700","wikidata":"https://www.wikidata.org/wiki/Q5656403","display_name":"Hardware architecture","level":3,"score":0.4460398852825165},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.43805521726608276},{"id":"https://openalex.org/C179518139","wikidata":"https://www.wikidata.org/wiki/Q5140297","display_name":"Coding (social sciences)","level":2,"score":0.42897307872772217},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4243430495262146},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.20662176609039307},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20414286851882935},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.16805365681648254},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.12894970178604126},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.07947805523872375},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icip.2016.7532742","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icip.2016.7532742","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE International Conference on Image Processing (ICIP)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.5600000023841858,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W2018496562","https://openalex.org/W2041171873","https://openalex.org/W2044170988","https://openalex.org/W2049550856","https://openalex.org/W2073340838","https://openalex.org/W2085699367","https://openalex.org/W2094532954","https://openalex.org/W2135948127","https://openalex.org/W2295513214","https://openalex.org/W2332316162","https://openalex.org/W6680239642"],"related_works":["https://openalex.org/W2165367082","https://openalex.org/W1972641423","https://openalex.org/W2117342402","https://openalex.org/W2128735135","https://openalex.org/W1663661117","https://openalex.org/W3149845128","https://openalex.org/W1992393033","https://openalex.org/W2127392486","https://openalex.org/W2152652624","https://openalex.org/W2125591518"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,83,90],"hardware":[4,36,49],"design":[5,50],"for":[6,57,65],"the":[7,23,73],"sub-sample":[8],"interpolator":[9],"used":[10],"in":[11,53],"FME":[12],"(Fractional":[13],"Motion":[14],"Estimation)":[15],"and":[16,25,45,55,70],"MC":[17],"(Motion":[18],"Compensation)":[19],"stages":[20],"according":[21],"to":[22,34,78],"VP9":[24],"VP10":[26],"video-coding":[27],"standards.":[28],"The":[29,48,60],"proposed":[30],"architecture":[31,75],"is":[32,76],"able":[33,77],"save":[35],"resources":[37],"through":[38],"an":[39],"optimized-filter":[40],"organization":[41],"whereas":[42],"reaching":[43],"high-throughput":[44],"low-power":[46],"dissipation.":[47],"was":[51],"described":[52],"Verilog":[54],"synthesized":[56],"ASIC":[58],"technology.":[59],"synthesis":[61],"results":[62],"were":[63],"generated":[64],"45nm":[66],"Nangate":[67],"standard":[68],"cells":[69],"demonstrate":[71],"that":[72],"developed":[74],"process":[79],"2160p@60fps":[80],"videos":[81],"with":[82],"power":[84],"dissipation":[85],"of":[86],"2.34mW":[87],"focusing":[88],"on":[89],"VP9-10":[91],"decoder.":[92]},"counts_by_year":[{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}