{"id":"https://openalex.org/W2782754928","doi":"https://doi.org/10.1109/iciinfs.2016.8262959","title":"Performance parameters optimization and implementation of adder/subtractor circuit using reversible logic approach","display_name":"Performance parameters optimization and implementation of adder/subtractor circuit using reversible logic approach","publication_year":2016,"publication_date":"2016-12-01","ids":{"openalex":"https://openalex.org/W2782754928","doi":"https://doi.org/10.1109/iciinfs.2016.8262959","mag":"2782754928"},"language":"en","primary_location":{"id":"doi:10.1109/iciinfs.2016.8262959","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iciinfs.2016.8262959","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 11th International Conference on Industrial and Information Systems (ICIIS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5059498373","display_name":"Vandana Shukla","orcid":"https://orcid.org/0000-0002-0523-1540"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Vandana Shukla","raw_affiliation_strings":["Amity School of Engineering & Technology, Amity University Uttar Pradesh, India"],"affiliations":[{"raw_affiliation_string":"Amity School of Engineering & Technology, Amity University Uttar Pradesh, India","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101986367","display_name":"O. P. Singh","orcid":"https://orcid.org/0000-0002-9946-4141"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"O. P. Singh","raw_affiliation_strings":["Amity School of Engineering & Technology, Amity University Uttar Pradesh, India"],"affiliations":[{"raw_affiliation_string":"Amity School of Engineering & Technology, Amity University Uttar Pradesh, India","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5086813280","display_name":"G. R. Mishra","orcid":"https://orcid.org/0000-0003-1211-3558"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"G. R. Mishra","raw_affiliation_strings":["Amity School of Engineering & Technology, Amity University Uttar Pradesh, India"],"affiliations":[{"raw_affiliation_string":"Amity School of Engineering & Technology, Amity University Uttar Pradesh, India","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5006905292","display_name":"Raj K. Tiwari","orcid":"https://orcid.org/0000-0001-7373-4679"},"institutions":[{"id":"https://openalex.org/I1337315214","display_name":"Dr. Ram Manohar Lohia Avadh University","ror":"https://ror.org/02797hn66","country_code":"IN","type":"education","lineage":["https://openalex.org/I1337315214"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"R. K. Tiwari","raw_affiliation_strings":["Department of Physics and Electronics, Dr. R. M. L. Avadh University, Faizabad, India"],"affiliations":[{"raw_affiliation_string":"Department of Physics and Electronics, Dr. R. M. L. Avadh University, Faizabad, India","institution_ids":["https://openalex.org/I1337315214"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5059498373"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.4285,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.81713719,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"323","last_page":"328"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10682","display_name":"Quantum Computing Algorithms and Architecture","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10682","display_name":"Quantum Computing Algorithms and Architecture","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13182","display_name":"Quantum-Dot Cellular Automata","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10020","display_name":"Quantum Information and Cryptography","score":0.9908999800682068,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/subtractor","display_name":"Subtractor","score":0.9288875460624695},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.8639092445373535},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6960386037826538},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.6204121112823486},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.4930085837841034},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4631798565387726},{"id":"https://openalex.org/keywords/truth-table","display_name":"Truth table","score":0.44062158465385437},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.43755170702934265},{"id":"https://openalex.org/keywords/quantum-computer","display_name":"Quantum computer","score":0.4352089464664459},{"id":"https://openalex.org/keywords/logic-block","display_name":"Logic block","score":0.4293639361858368},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.4228825867176056},{"id":"https://openalex.org/keywords/reversible-computing","display_name":"Reversible computing","score":0.41963332891464233},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4050474166870117},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3662848472595215},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.25649118423461914},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.21179452538490295},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.20101386308670044},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.17591255903244019},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15307331085205078},{"id":"https://openalex.org/keywords/quantum","display_name":"Quantum","score":0.0911281406879425},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.0732521116733551}],"concepts":[{"id":"https://openalex.org/C187805909","wikidata":"https://www.wikidata.org/wiki/Q1142401","display_name":"Subtractor","level":4,"score":0.9288875460624695},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.8639092445373535},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6960386037826538},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.6204121112823486},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.4930085837841034},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4631798565387726},{"id":"https://openalex.org/C56949724","wikidata":"https://www.wikidata.org/wiki/Q219079","display_name":"Truth table","level":2,"score":0.44062158465385437},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.43755170702934265},{"id":"https://openalex.org/C58053490","wikidata":"https://www.wikidata.org/wiki/Q176555","display_name":"Quantum computer","level":3,"score":0.4352089464664459},{"id":"https://openalex.org/C2778325283","wikidata":"https://www.wikidata.org/wiki/Q1125244","display_name":"Logic block","level":3,"score":0.4293639361858368},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.4228825867176056},{"id":"https://openalex.org/C20274610","wikidata":"https://www.wikidata.org/wiki/Q185410","display_name":"Reversible computing","level":4,"score":0.41963332891464233},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4050474166870117},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3662848472595215},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.25649118423461914},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.21179452538490295},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.20101386308670044},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.17591255903244019},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15307331085205078},{"id":"https://openalex.org/C84114770","wikidata":"https://www.wikidata.org/wiki/Q46344","display_name":"Quantum","level":2,"score":0.0911281406879425},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0732521116733551},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iciinfs.2016.8262959","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iciinfs.2016.8262959","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 11th International Conference on Industrial and Information Systems (ICIIS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":50,"referenced_works":["https://openalex.org/W83476284","https://openalex.org/W93437325","https://openalex.org/W1480114417","https://openalex.org/W1551569459","https://openalex.org/W1558321034","https://openalex.org/W1964976896","https://openalex.org/W1965854837","https://openalex.org/W1978293322","https://openalex.org/W1988422312","https://openalex.org/W2001236151","https://openalex.org/W2002086086","https://openalex.org/W2003989103","https://openalex.org/W2034704469","https://openalex.org/W2037753698","https://openalex.org/W2054495961","https://openalex.org/W2056896932","https://openalex.org/W2059041305","https://openalex.org/W2061152750","https://openalex.org/W2069684819","https://openalex.org/W2069825906","https://openalex.org/W2077603079","https://openalex.org/W2105259569","https://openalex.org/W2120475651","https://openalex.org/W2124236732","https://openalex.org/W2137760991","https://openalex.org/W2146091490","https://openalex.org/W2151292904","https://openalex.org/W2159848982","https://openalex.org/W2162556901","https://openalex.org/W2162769381","https://openalex.org/W2163011756","https://openalex.org/W2181643515","https://openalex.org/W2185876773","https://openalex.org/W2188780046","https://openalex.org/W2343310090","https://openalex.org/W2912120411","https://openalex.org/W2912318510","https://openalex.org/W4231932287","https://openalex.org/W4233798822","https://openalex.org/W4246625483","https://openalex.org/W4251109627","https://openalex.org/W6603376720","https://openalex.org/W6603783165","https://openalex.org/W6628784724","https://openalex.org/W6633370444","https://openalex.org/W6682816755","https://openalex.org/W6683964127","https://openalex.org/W6686071995","https://openalex.org/W6686915839","https://openalex.org/W6687258038"],"related_works":["https://openalex.org/W2065303046","https://openalex.org/W2212614118","https://openalex.org/W1564210455","https://openalex.org/W2294621766","https://openalex.org/W1929924975","https://openalex.org/W3134326786","https://openalex.org/W2544896136","https://openalex.org/W2116607558","https://openalex.org/W4285325337","https://openalex.org/W2465495808"],"abstract_inverted_index":{"Arithmetic":[0],"digital":[1],"processing":[2,43,192],"sub-systems":[3],"are":[4,45,85],"considered":[5],"as":[6,30,132],"one":[7,21],"of":[8,12,22,26,34,39,49,65,87,94,135,148,179,189],"the":[9,23,46,50,55,63,88,92,95,140,149,153,187],"major":[10],"component":[11],"any":[13,35],"electronic":[14],"computing":[15,27,81],"system.":[16],"The":[17,118],"adder/subtractor":[18,110],"circuit":[19,67,159,182],"is":[20,54,121,163],"vital":[24],"part":[25],"systems":[28],"such":[29,131],"arithmetic":[31],"logic":[32,97,115],"unit":[33],"computer.":[36],"Moreover,":[37],"urge":[38],"efficient":[40],"low":[41,190],"loss":[42],"devices":[44],"basic":[47,56],"need":[48,53],"time.":[51],"This":[52],"motivation":[57],"for":[58,167,186],"researchers":[59],"to":[60,107],"progress":[61],"in":[62,139],"field":[64],"reversible":[66,96,114,136,161],"design":[68,108,120,155],"approach.":[69],"Low":[70],"power":[71,191],"VLSI":[72],"circuits,":[73],"DNA":[74],"computing,":[75,77],"optical":[76],"signal":[78],"processing,":[79],"quantum":[80,146],"and":[82,145,165],"nanotechnology":[83],"etc.":[84],"some":[86,128],"progressive":[89],"fields":[90],"with":[91,112,123,171,174],"application":[93],"concepts.":[98],"In":[99],"this":[100,180],"paper,":[101],"we":[102],"have":[103],"proposed":[104,119,154],"an":[105],"approach":[106,162],"n-bit":[109],"circuits":[111],"available":[113],"gates":[116,137],"only.":[117],"compared":[122],"existing":[124],"designs":[125],"based":[126],"on":[127,152],"selected":[129],"factors":[130],"total":[133],"number":[134],"used":[138],"design,":[141],"garbage":[142],"outputs":[143],"generated":[144],"cost":[147],"design.":[150],"Based":[151],"approach,":[156],"8-bit":[157],"adder-subtractor":[158],"using":[160],"simulated":[164],"synthesised":[166],"Xilinx":[168],"Spartan":[169],"3E":[170],"Device":[172],"XC3S500E":[173],"200":[175],"MHz":[176],"frequency.":[177],"Application":[178],"optimized":[181],"may":[183],"be":[184],"visualized":[185],"designing":[188],"devices.":[193]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}