{"id":"https://openalex.org/W2783610420","doi":"https://doi.org/10.1109/iciinfs.2016.8262929","title":"Analysis and design of single ended SRAM cell for low-power operation","display_name":"Analysis and design of single ended SRAM cell for low-power operation","publication_year":2016,"publication_date":"2016-12-01","ids":{"openalex":"https://openalex.org/W2783610420","doi":"https://doi.org/10.1109/iciinfs.2016.8262929","mag":"2783610420"},"language":"en","primary_location":{"id":"doi:10.1109/iciinfs.2016.8262929","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iciinfs.2016.8262929","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 11th International Conference on Industrial and Information Systems (ICIIS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5062442933","display_name":"Sunil Kumar Ojha","orcid":"https://orcid.org/0000-0002-8969-041X"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Sunil Kumar Ojha","raw_affiliation_strings":["Department of Electronics, Amity University, Lucknow, India"],"affiliations":[{"raw_affiliation_string":"Department of Electronics, Amity University, Lucknow, India","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101986367","display_name":"O. P. Singh","orcid":"https://orcid.org/0000-0002-9946-4141"},"institutions":[{"id":"https://openalex.org/I24676775","display_name":"Indian Institute of Technology Madras","ror":"https://ror.org/03v0r5n49","country_code":"IN","type":"facility","lineage":["https://openalex.org/I24676775"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"O. P. Singh","raw_affiliation_strings":["Retd. Prof. Department of Electrical Engineering, Indian Institute of Technology, Madras, India"],"affiliations":[{"raw_affiliation_string":"Retd. Prof. Department of Electrical Engineering, Indian Institute of Technology, Madras, India","institution_ids":["https://openalex.org/I24676775"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5086813280","display_name":"G. R. Mishra","orcid":"https://orcid.org/0000-0003-1211-3558"},"institutions":[{"id":"https://openalex.org/I24676775","display_name":"Indian Institute of Technology Madras","ror":"https://ror.org/03v0r5n49","country_code":"IN","type":"facility","lineage":["https://openalex.org/I24676775"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"G. R. Mishra","raw_affiliation_strings":["Retd. Prof. Department of Electrical Engineering, Indian Institute of Technology, Madras, India"],"affiliations":[{"raw_affiliation_string":"Retd. Prof. Department of Electrical Engineering, Indian Institute of Technology, Madras, India","institution_ids":["https://openalex.org/I24676775"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5021115912","display_name":"P. R. Vaya","orcid":null},"institutions":[{"id":"https://openalex.org/I24676775","display_name":"Indian Institute of Technology Madras","ror":"https://ror.org/03v0r5n49","country_code":"IN","type":"facility","lineage":["https://openalex.org/I24676775"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"P. R. Vaya","raw_affiliation_strings":["Retd. Prof. Department of Electrical Engineering, Indian Institute of Technology, Madras, India"],"affiliations":[{"raw_affiliation_string":"Retd. Prof. Department of Electrical Engineering, Indian Institute of Technology, Madras, India","institution_ids":["https://openalex.org/I24676775"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5062442933"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.1838,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.6240648,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"178","last_page":"181"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.7376807332038879},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.6222320199012756},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.5740363597869873},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5394479036331177},{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.48364436626434326},{"id":"https://openalex.org/keywords/memory-cell","display_name":"Memory cell","score":0.42318564653396606},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.41048258543014526},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4068748950958252},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3589242696762085},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2797635495662689}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.7376807332038879},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.6222320199012756},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.5740363597869873},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5394479036331177},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.48364436626434326},{"id":"https://openalex.org/C2776638159","wikidata":"https://www.wikidata.org/wiki/Q18343761","display_name":"Memory cell","level":4,"score":0.42318564653396606},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.41048258543014526},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4068748950958252},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3589242696762085},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2797635495662689},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iciinfs.2016.8262929","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iciinfs.2016.8262929","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 11th International Conference on Industrial and Information Systems (ICIIS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8700000047683716,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1974159394","https://openalex.org/W1984048874","https://openalex.org/W2000410358","https://openalex.org/W2034162494","https://openalex.org/W2035589388","https://openalex.org/W2101640694","https://openalex.org/W2105175332","https://openalex.org/W2114330343","https://openalex.org/W2127734757","https://openalex.org/W2129998592","https://openalex.org/W2158018705","https://openalex.org/W2546231500","https://openalex.org/W3142526730","https://openalex.org/W6643625309","https://openalex.org/W6658973214"],"related_works":["https://openalex.org/W2022118530","https://openalex.org/W2158870714","https://openalex.org/W3133428823","https://openalex.org/W2112776829","https://openalex.org/W1504951709","https://openalex.org/W4323831463","https://openalex.org/W2105010454","https://openalex.org/W3202758229","https://openalex.org/W2372710105","https://openalex.org/W2915176329"],"abstract_inverted_index":{"In":[0],"current":[1],"developments":[2],"of":[3,10,50,64,97,109,114,124,132,159,185,195,213,221,230],"semiconductor":[4],"memory":[5,14],"cell":[6,15,55,71,99,126,134,143,167,197,235],"design":[7,83,147],"specially":[8],"designing":[9],"static":[11],"random":[12],"access":[13],"is":[16,30,136,162,180,205],"become":[17],"a":[18,51,85,137],"major":[19],"critical":[20,138],"issue,":[21],"due":[22],"to":[23,32,163],"the":[24,27,39,48,62,65,67,81,90,98,102,106,110,118,125,130,133,141,149,165,183,191,196,210,217,222,228,231],"fact":[25],"that":[26],"process":[28],"technology":[29,179],"scaling":[31],"newer":[33],"node":[34],"very":[35],"rapidly":[36],"and":[37,121,171],"hence":[38],"transistor":[40,151],"size":[41],"reduces":[42,101],"most":[43],"frequently.":[44],"This":[45,112],"paper":[46],"analyzes":[47],"performance":[49,229],"single":[52,68,86,232],"ended":[53,69,233],"SRAM":[54,70,142,166,234],"for":[56,89,105,140,153,236],"low":[57,173,192,218,237,241],"power":[58,76,103,193,204,211,219,238],"operation.":[59,155,243],"As":[60],"per":[61],"state":[63],"art":[66],"should":[72],"operate":[73,164],"at":[74],"lowest":[75],"supply":[77,212],"as":[78,92,94,207],"possible":[79],"so":[80],"presented":[82],"uses":[84],"bit":[87],"line":[88],"read":[91,119],"well":[93],"writes":[95,122],"operation":[96,108,115,194,220,239],"which":[100,127,135,215],"requirements":[104],"proper":[107,169],"cell.":[111,223],"type":[113],"also":[116],"improves":[117,129],"stability":[120,131,170],"ability":[123],"overall":[128],"factor":[139],"designing.":[144],"The":[145,156,175,187,201],"proposed":[146],"has":[148],"enhanced":[150],"models":[152],"efficient":[154],"main":[157],"objective":[158],"this":[160,225],"work":[161,226],"with":[168,172,198,209,240],"voltage.":[174],"standard":[176],"90nm":[177],"processes":[178],"used":[181],"in":[182],"modeling":[184],"transistors.":[186],"simulation":[188],"result":[189],"shows":[190,216],"improved":[199],"stability.":[200],"average":[202],"transition":[203],"obtained":[206],"1.1\u03bcw":[208],"1.6v":[214],"Thus":[224],"evaluates":[227],"voltage":[242]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
