{"id":"https://openalex.org/W4308274236","doi":"https://doi.org/10.1109/icicdt56182.2022.9933106","title":"A Low-Energy 8-bit CLA Realized by Single-Phase ANT Logic","display_name":"A Low-Energy 8-bit CLA Realized by Single-Phase ANT Logic","publication_year":2022,"publication_date":"2022-09-21","ids":{"openalex":"https://openalex.org/W4308274236","doi":"https://doi.org/10.1109/icicdt56182.2022.9933106"},"language":"en","primary_location":{"id":"doi:10.1109/icicdt56182.2022.9933106","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icicdt56182.2022.9933106","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 International Conference on IC Design and Technology (ICICDT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5048139637","display_name":"Durga Srikanth Kamarajugadda","orcid":null},"institutions":[{"id":"https://openalex.org/I142974352","display_name":"National Sun Yat-sen University","ror":"https://ror.org/00mjawt10","country_code":"TW","type":"education","lineage":["https://openalex.org/I142974352"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Durga Srikanth Kamarajugadda","raw_affiliation_strings":["National Sun Yat-Sen University,Dept. of Electrical Eng.,Kaohsiung,Taiwan,80424"],"affiliations":[{"raw_affiliation_string":"National Sun Yat-Sen University,Dept. of Electrical Eng.,Kaohsiung,Taiwan,80424","institution_ids":["https://openalex.org/I142974352"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5058562624","display_name":"Oliver Lexter July A. Jose","orcid":"https://orcid.org/0000-0003-4565-9506"},"institutions":[{"id":"https://openalex.org/I3516337","display_name":"Batangas State University","ror":"https://ror.org/019en2y21","country_code":"PH","type":"education","lineage":["https://openalex.org/I3516337"]},{"id":"https://openalex.org/I142974352","display_name":"National Sun Yat-sen University","ror":"https://ror.org/00mjawt10","country_code":"TW","type":"education","lineage":["https://openalex.org/I142974352"]}],"countries":["PH","TW"],"is_corresponding":false,"raw_author_name":"Oliver Lexter July A. Jose","raw_affiliation_strings":["National Sun Yat-Sen University,Dept. of Electrical Eng.,Kaohsiung,Taiwan,80424","Dept. of Electronics Engineering, Batangas State University, The National Engineering University, Philippines"],"affiliations":[{"raw_affiliation_string":"National Sun Yat-Sen University,Dept. of Electrical Eng.,Kaohsiung,Taiwan,80424","institution_ids":["https://openalex.org/I142974352"]},{"raw_affiliation_string":"Dept. of Electronics Engineering, Batangas State University, The National Engineering University, Philippines","institution_ids":["https://openalex.org/I3516337"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5078382713","display_name":"Lung\u2010Jieh Yang","orcid":"https://orcid.org/0000-0002-0639-0973"},"institutions":[{"id":"https://openalex.org/I107470533","display_name":"Tamkang University","ror":"https://ror.org/04tft4718","country_code":"TW","type":"education","lineage":["https://openalex.org/I107470533"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Lung-Jieh Yang","raw_affiliation_strings":["Tamkang University,Dept. of Mech. &#x0026; Electromech. Eng.,Taipei,Taiwan,10650"],"affiliations":[{"raw_affiliation_string":"Tamkang University,Dept. of Mech. &#x0026; Electromech. Eng.,Taipei,Taiwan,10650","institution_ids":["https://openalex.org/I107470533"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5045841076","display_name":"Balasubramanian Esakki","orcid":"https://orcid.org/0000-0003-4663-4132"},"institutions":[{"id":"https://openalex.org/I1330855593","display_name":"Vel Tech Rangarajan Dr. Sagunthala R&D Institute of Science and Technology","ror":"https://ror.org/05bc5bx80","country_code":"IN","type":"education","lineage":["https://openalex.org/I1330855593"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Balasubramanian Esakki","raw_affiliation_strings":["Vel Tech University,Dept. of Mechanical Eng.,Chennai,India,600062"],"affiliations":[{"raw_affiliation_string":"Vel Tech University,Dept. of Mechanical Eng.,Chennai,India,600062","institution_ids":["https://openalex.org/I1330855593"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5004485824","display_name":"Sivaperumal Sampath","orcid":null},"institutions":[{"id":"https://openalex.org/I157674215","display_name":"Presidency University","ror":"https://ror.org/04xgbph11","country_code":"IN","type":"education","lineage":["https://openalex.org/I157674215"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Sivaperumal Sampath","raw_affiliation_strings":["Presidency University,Dept. of Electronics &#x0026; Comm. Eng.,Bengaluru,India,560064"],"affiliations":[{"raw_affiliation_string":"Presidency University,Dept. of Electronics &#x0026; Comm. Eng.,Bengaluru,India,560064","institution_ids":["https://openalex.org/I157674215"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5077220045","display_name":"Chua\u2010Chin Wang","orcid":"https://orcid.org/0000-0002-2426-2879"},"institutions":[{"id":"https://openalex.org/I142974352","display_name":"National Sun Yat-sen University","ror":"https://ror.org/00mjawt10","country_code":"TW","type":"education","lineage":["https://openalex.org/I142974352"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chua-Chin Wang","raw_affiliation_strings":["National Sun Yat-Sen University,Dept. of Electrical Eng.,Kaohsiung,Taiwan,80424","Ins. of Undersea Technology, National Sun Yat-Sen University, Taiwan"],"affiliations":[{"raw_affiliation_string":"National Sun Yat-Sen University,Dept. of Electrical Eng.,Kaohsiung,Taiwan,80424","institution_ids":["https://openalex.org/I142974352"]},{"raw_affiliation_string":"Ins. of Undersea Technology, National Sun Yat-Sen University, Taiwan","institution_ids":["https://openalex.org/I142974352"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5048139637"],"corresponding_institution_ids":["https://openalex.org/I142974352"],"apc_list":null,"apc_paid":null,"fwci":0.0801,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.36182632,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"28","last_page":"31"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.6989739537239075},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6221703886985779},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5739690065383911},{"id":"https://openalex.org/keywords/capacitance","display_name":"Capacitance","score":0.5373209118843079},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5354376435279846},{"id":"https://openalex.org/keywords/dissipation","display_name":"Dissipation","score":0.514898419380188},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.503231942653656},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.47917118668556213},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4723718464374542},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4722000062465668},{"id":"https://openalex.org/keywords/logic-level","display_name":"Logic level","score":0.47045600414276123},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.45448020100593567},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.41604968905448914},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.36799728870391846},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.36632248759269714},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3651484549045563},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.24414169788360596},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23716679215431213},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.10736814141273499},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.10081803798675537}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.6989739537239075},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6221703886985779},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5739690065383911},{"id":"https://openalex.org/C30066665","wikidata":"https://www.wikidata.org/wiki/Q164399","display_name":"Capacitance","level":3,"score":0.5373209118843079},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5354376435279846},{"id":"https://openalex.org/C135402231","wikidata":"https://www.wikidata.org/wiki/Q898440","display_name":"Dissipation","level":2,"score":0.514898419380188},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.503231942653656},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.47917118668556213},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4723718464374542},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4722000062465668},{"id":"https://openalex.org/C146569638","wikidata":"https://www.wikidata.org/wiki/Q173378","display_name":"Logic level","level":3,"score":0.47045600414276123},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.45448020100593567},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.41604968905448914},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.36799728870391846},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.36632248759269714},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3651484549045563},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.24414169788360596},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23716679215431213},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.10736814141273499},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.10081803798675537},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C17525397","wikidata":"https://www.wikidata.org/wiki/Q176140","display_name":"Electrode","level":2,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C97355855","wikidata":"https://www.wikidata.org/wiki/Q11473","display_name":"Thermodynamics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icicdt56182.2022.9933106","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icicdt56182.2022.9933106","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 International Conference on IC Design and Technology (ICICDT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8799999952316284,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320309618","display_name":"Ministry of Science and Technology","ror":"https://ror.org/02b207r52"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W2055164866","https://openalex.org/W2124278579","https://openalex.org/W2140077908","https://openalex.org/W2140958423","https://openalex.org/W2803057706","https://openalex.org/W3011688954","https://openalex.org/W3118472427","https://openalex.org/W4210623756"],"related_works":["https://openalex.org/W1485027372","https://openalex.org/W2586049422","https://openalex.org/W2916239311","https://openalex.org/W2548259017","https://openalex.org/W1958405720","https://openalex.org/W2338212935","https://openalex.org/W2516103912","https://openalex.org/W1994123863","https://openalex.org/W2490163188","https://openalex.org/W2159435335"],"abstract_inverted_index":{"Low":[0],"power":[1,30,88],"and":[2,31,41,49,97],"high-speed":[3],"carry":[4],"look-ahead":[5],"adder":[6],"(CLA)":[7],"is":[8,35,60,90,101],"one":[9],"of":[10,68,74],"the":[11,47,54,65,87,98],"most":[12],"demanded":[13],"digital":[14],"computation":[15],"units.":[16],"This":[17],"paper":[18],"demonstrates":[19],"a":[20,72,93],"CLA":[21],"based":[22],"on":[23],"single-phase":[24],"ANT":[25],"logic":[26],"to":[27,45,62],"achieve":[28],"low":[29],"high":[32],"speed.":[33],"It":[34],"featured":[36],"with":[37,71,92],"load":[38,73],"capacitance":[39],"reduction":[40],"no":[42],"internal":[43],"loop":[44],"enhance":[46],"speed":[48],"reduce":[50],"switching":[51],"activity":[52],"at":[53,64],"same":[55],"time.":[56],"The":[57],"proposed":[58],"design":[59],"proved":[61],"work":[63],"clock":[66],"frequency":[67],"20":[69],"GHz":[70],"60":[75],"pF":[76],"implemented":[77],"using":[78],"40":[79],"nm":[80],"CMOS":[81],"technology":[82],"by":[83],"post-layout":[84],"simulations,":[85],"where":[86],"dissipation":[89],"observed":[91],"normalized":[94,99],"0.071":[95],"mW":[96],"PDP":[100],"0.08":[102],"pJ.":[103]},"counts_by_year":[{"year":2024,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
