{"id":"https://openalex.org/W2967046827","doi":"https://doi.org/10.1109/icicdt.2019.8790834","title":"A Write-Verification Method for Non-Volatile Memory","display_name":"A Write-Verification Method for Non-Volatile Memory","publication_year":2019,"publication_date":"2019-06-01","ids":{"openalex":"https://openalex.org/W2967046827","doi":"https://doi.org/10.1109/icicdt.2019.8790834","mag":"2967046827"},"language":"en","primary_location":{"id":"doi:10.1109/icicdt.2019.8790834","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icicdt.2019.8790834","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 International Conference on IC Design and Technology (ICICDT)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100773050","display_name":"Yiping Zhang","orcid":"https://orcid.org/0000-0002-3340-2378"},"institutions":[{"id":"https://openalex.org/I3923682","display_name":"Soochow University","ror":"https://ror.org/05t8y2r12","country_code":"CN","type":"education","lineage":["https://openalex.org/I3923682"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yiping Zhang","raw_affiliation_strings":["School of Urban rail transportation, Soochow University, Suzhou, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Urban rail transportation, Soochow University, Suzhou, China","institution_ids":["https://openalex.org/I3923682"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103826983","display_name":"Canyan Zhu","orcid":null},"institutions":[{"id":"https://openalex.org/I3923682","display_name":"Soochow University","ror":"https://ror.org/05t8y2r12","country_code":"CN","type":"education","lineage":["https://openalex.org/I3923682"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Canyan Zhu","raw_affiliation_strings":["School of Urban rail transportation, Soochow University, Suzhou, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Urban rail transportation, Soochow University, Suzhou, China","institution_ids":["https://openalex.org/I3923682"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100448153","display_name":"Lijun Zhang","orcid":"https://orcid.org/0000-0002-3692-2088"},"institutions":[{"id":"https://openalex.org/I3923682","display_name":"Soochow University","ror":"https://ror.org/05t8y2r12","country_code":"CN","type":"education","lineage":["https://openalex.org/I3923682"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Lijun Zhang","raw_affiliation_strings":["School of Urban rail transportation, Soochow University, Suzhou, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Urban rail transportation, Soochow University, Suzhou, China","institution_ids":["https://openalex.org/I3923682"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5054254499","display_name":"Ziou Wang","orcid":null},"institutions":[{"id":"https://openalex.org/I3923682","display_name":"Soochow University","ror":"https://ror.org/05t8y2r12","country_code":"CN","type":"education","lineage":["https://openalex.org/I3923682"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Ziou Wang","raw_affiliation_strings":["School of electronic and information engineering, Soochow University, Suzhou, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of electronic and information engineering, Soochow University, Suzhou, China","institution_ids":["https://openalex.org/I3923682"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I3923682"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"3"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/resistive-random-access-memory","display_name":"Resistive random-access memory","score":0.7736749053001404},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7693547010421753},{"id":"https://openalex.org/keywords/non-volatile-memory","display_name":"Non-volatile memory","score":0.7339257001876831},{"id":"https://openalex.org/keywords/magnetoresistive-random-access-memory","display_name":"Magnetoresistive random-access memory","score":0.5896185040473938},{"id":"https://openalex.org/keywords/random-access-memory","display_name":"Random access memory","score":0.5158554911613464},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.4838953912258148},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.48125430941581726},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.45760273933410645},{"id":"https://openalex.org/keywords/internet-of-things","display_name":"Internet of Things","score":0.4570794403553009},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.42292284965515137},{"id":"https://openalex.org/keywords/memory-refresh","display_name":"Memory refresh","score":0.4103664755821228},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.39927467703819275},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.36601150035858154},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3598978519439697},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.35876917839050293},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.17710399627685547},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.08459910750389099},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.07679176330566406},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.05765455961227417}],"concepts":[{"id":"https://openalex.org/C182019814","wikidata":"https://www.wikidata.org/wiki/Q1143830","display_name":"Resistive random-access memory","level":3,"score":0.7736749053001404},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7693547010421753},{"id":"https://openalex.org/C177950962","wikidata":"https://www.wikidata.org/wiki/Q10997658","display_name":"Non-volatile memory","level":2,"score":0.7339257001876831},{"id":"https://openalex.org/C46891859","wikidata":"https://www.wikidata.org/wiki/Q1061546","display_name":"Magnetoresistive random-access memory","level":3,"score":0.5896185040473938},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.5158554911613464},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.4838953912258148},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.48125430941581726},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.45760273933410645},{"id":"https://openalex.org/C81860439","wikidata":"https://www.wikidata.org/wiki/Q251212","display_name":"Internet of Things","level":2,"score":0.4570794403553009},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.42292284965515137},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.4103664755821228},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.39927467703819275},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.36601150035858154},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3598978519439697},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.35876917839050293},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.17710399627685547},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.08459910750389099},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.07679176330566406},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.05765455961227417},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icicdt.2019.8790834","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icicdt.2019.8790834","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 International Conference on IC Design and Technology (ICICDT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.5400000214576721,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W2031559328","https://openalex.org/W2168602049","https://openalex.org/W2345292415","https://openalex.org/W2567355330","https://openalex.org/W2762231242","https://openalex.org/W6705002894"],"related_works":["https://openalex.org/W4242495027","https://openalex.org/W2100773763","https://openalex.org/W2898989424","https://openalex.org/W4285257158","https://openalex.org/W2011581354","https://openalex.org/W3096220267","https://openalex.org/W3209704453","https://openalex.org/W1977284748","https://openalex.org/W2065778483","https://openalex.org/W2024190459"],"abstract_inverted_index":{"With":[0],"the":[1,19,22,54,66,92],"fast":[2],"development":[3],"in":[4,43],"IOT":[5],"(Internet":[6],"Of":[7],"Things)":[8],"and":[9,50,72],"portable":[10],"intelligent":[11],"product":[12],"markets,":[13],"VLSI":[14],"continually":[15],"scales":[16],"down.":[17],"As":[18],"candidates":[20],"for":[21,88,95],"small":[23],"scale":[24],"memory,":[25],"several":[26],"new":[27,75],"types":[28],"of":[29],"non-volatile":[30],"memory":[31,33],"(NVM)":[32],"such":[34],"as":[35],"RRAM,":[36],"MRAM,":[37],"PRAM":[38],"have":[39],"made":[40],"great":[41],"process":[42],"these":[44],"years.":[45],"Their":[46],"area,":[47],"work":[48],"speed,":[49],"application":[51],"flexibility":[52],"are":[53],"advantage":[55],"compared":[56],"with":[57],"traditional":[58],"NVM.":[59],"In":[60],"this":[61,80],"paper,":[62],"we":[63,82],"focus":[64],"on":[65],"Resistor":[67],"Random":[68],"Access":[69],"Memory":[70],"(RRAM)":[71],"propose":[73],"a":[74,85],"write":[76,89,93],"verification":[77],"technique.":[78],"By":[79],"method,":[81],"can":[83,97],"achieve":[84],"high":[86],"reliability":[87],"access.":[90],"Also":[91],"scheme":[94],"RRAM":[96],"be":[98],"simplified.":[99]},"counts_by_year":[{"year":2025,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}