{"id":"https://openalex.org/W2012278691","doi":"https://doi.org/10.1109/icicdt.2012.6232874","title":"Unifying design data during verification: Implementing Logic-Driven Layout analysis and debug","display_name":"Unifying design data during verification: Implementing Logic-Driven Layout analysis and debug","publication_year":2012,"publication_date":"2012-05-01","ids":{"openalex":"https://openalex.org/W2012278691","doi":"https://doi.org/10.1109/icicdt.2012.6232874","mag":"2012278691"},"language":"en","primary_location":{"id":"doi:10.1109/icicdt.2012.6232874","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icicdt.2012.6232874","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE International Conference on IC Design & Technology","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5031199055","display_name":"Kishore Kollu","orcid":null},"institutions":[{"id":"https://openalex.org/I105695857","display_name":"Siemens (Hungary)","ror":"https://ror.org/01rk7mv85","country_code":"HU","type":"company","lineage":["https://openalex.org/I105695857","https://openalex.org/I1325886976"]}],"countries":["HU"],"is_corresponding":true,"raw_author_name":"Kishore Kollu","raw_affiliation_strings":["Design to Silicon Division, Mentor Graphics, Wilsonville, OR, USA","Design to Silicon Division, Mentor Graphics, Wilsonville, OR USA"],"affiliations":[{"raw_affiliation_string":"Design to Silicon Division, Mentor Graphics, Wilsonville, OR, USA","institution_ids":["https://openalex.org/I105695857"]},{"raw_affiliation_string":"Design to Silicon Division, Mentor Graphics, Wilsonville, OR USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5004015839","display_name":"Trey D Jackson","orcid":"https://orcid.org/0000-0001-8457-6389"},"institutions":[{"id":"https://openalex.org/I105695857","display_name":"Siemens (Hungary)","ror":"https://ror.org/01rk7mv85","country_code":"HU","type":"company","lineage":["https://openalex.org/I105695857","https://openalex.org/I1325886976"]}],"countries":["HU"],"is_corresponding":false,"raw_author_name":"Trey Jackson","raw_affiliation_strings":["Design to Silicon Division, Mentor Graphics, Wilsonville, OR, USA","Design to Silicon Division, Mentor Graphics, Wilsonville, OR USA"],"affiliations":[{"raw_affiliation_string":"Design to Silicon Division, Mentor Graphics, Wilsonville, OR, USA","institution_ids":["https://openalex.org/I105695857"]},{"raw_affiliation_string":"Design to Silicon Division, Mentor Graphics, Wilsonville, OR USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5058973691","display_name":"Farhad Kharas","orcid":null},"institutions":[{"id":"https://openalex.org/I105695857","display_name":"Siemens (Hungary)","ror":"https://ror.org/01rk7mv85","country_code":"HU","type":"company","lineage":["https://openalex.org/I105695857","https://openalex.org/I1325886976"]}],"countries":["HU"],"is_corresponding":false,"raw_author_name":"Farhad Kharas","raw_affiliation_strings":["Design to Silicon Division, Mentor Graphics, Wilsonville, OR, USA","Design to Silicon Division, Mentor Graphics, Wilsonville, OR USA"],"affiliations":[{"raw_affiliation_string":"Design to Silicon Division, Mentor Graphics, Wilsonville, OR, USA","institution_ids":["https://openalex.org/I105695857"]},{"raw_affiliation_string":"Design to Silicon Division, Mentor Graphics, Wilsonville, OR USA","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5091327472","display_name":"Anant Adke","orcid":null},"institutions":[{"id":"https://openalex.org/I105695857","display_name":"Siemens (Hungary)","ror":"https://ror.org/01rk7mv85","country_code":"HU","type":"company","lineage":["https://openalex.org/I105695857","https://openalex.org/I1325886976"]}],"countries":["HU"],"is_corresponding":false,"raw_author_name":"Anant Adke","raw_affiliation_strings":["Design to Silicon Division, Mentor Graphics, Wilsonville, OR, USA","Design to Silicon Division, Mentor Graphics, Wilsonville, OR USA"],"affiliations":[{"raw_affiliation_string":"Design to Silicon Division, Mentor Graphics, Wilsonville, OR, USA","institution_ids":["https://openalex.org/I105695857"]},{"raw_affiliation_string":"Design to Silicon Division, Mentor Graphics, Wilsonville, OR USA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5031199055"],"corresponding_institution_ids":["https://openalex.org/I105695857"],"apc_list":null,"apc_paid":null,"fwci":1.2451,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.81152203,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.7577357292175293},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7282823920249939},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.6795171499252319},{"id":"https://openalex.org/keywords/design-layout-record","display_name":"Design layout record","score":0.6569540500640869},{"id":"https://openalex.org/keywords/context","display_name":"Context (archaeology)","score":0.5652924180030823},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5511457920074463},{"id":"https://openalex.org/keywords/parametric-statistics","display_name":"Parametric statistics","score":0.4804620146751404},{"id":"https://openalex.org/keywords/logical-conjunction","display_name":"Logical conjunction","score":0.4765803813934326},{"id":"https://openalex.org/keywords/ic-layout-editor","display_name":"IC layout editor","score":0.4575653672218323},{"id":"https://openalex.org/keywords/domain","display_name":"Domain (mathematical analysis)","score":0.4540449380874634},{"id":"https://openalex.org/keywords/limiting","display_name":"Limiting","score":0.43516016006469727},{"id":"https://openalex.org/keywords/software-engineering","display_name":"Software engineering","score":0.3574613034725189},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.3435922861099243},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3418438136577606},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.29107314348220825},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.2387056052684784},{"id":"https://openalex.org/keywords/circuit-extraction","display_name":"Circuit extraction","score":0.20934432744979858},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1766580045223236},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.11403131484985352}],"concepts":[{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.7577357292175293},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7282823920249939},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.6795171499252319},{"id":"https://openalex.org/C179145894","wikidata":"https://www.wikidata.org/wiki/Q5264353","display_name":"Design layout record","level":5,"score":0.6569540500640869},{"id":"https://openalex.org/C2779343474","wikidata":"https://www.wikidata.org/wiki/Q3109175","display_name":"Context (archaeology)","level":2,"score":0.5652924180030823},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5511457920074463},{"id":"https://openalex.org/C117251300","wikidata":"https://www.wikidata.org/wiki/Q1849855","display_name":"Parametric statistics","level":2,"score":0.4804620146751404},{"id":"https://openalex.org/C21847791","wikidata":"https://www.wikidata.org/wiki/Q191081","display_name":"Logical conjunction","level":2,"score":0.4765803813934326},{"id":"https://openalex.org/C5546195","wikidata":"https://www.wikidata.org/wiki/Q5969842","display_name":"IC layout editor","level":5,"score":0.4575653672218323},{"id":"https://openalex.org/C36503486","wikidata":"https://www.wikidata.org/wiki/Q11235244","display_name":"Domain (mathematical analysis)","level":2,"score":0.4540449380874634},{"id":"https://openalex.org/C188198153","wikidata":"https://www.wikidata.org/wiki/Q1613840","display_name":"Limiting","level":2,"score":0.43516016006469727},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.3574613034725189},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.3435922861099243},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3418438136577606},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.29107314348220825},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.2387056052684784},{"id":"https://openalex.org/C26490066","wikidata":"https://www.wikidata.org/wiki/Q17006835","display_name":"Circuit extraction","level":4,"score":0.20934432744979858},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1766580045223236},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.11403131484985352},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C23572009","wikidata":"https://www.wikidata.org/wiki/Q964981","display_name":"Equivalent circuit","level":3,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icicdt.2012.6232874","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icicdt.2012.6232874","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE International Conference on IC Design & Technology","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.4399999976158142,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W2123047626","https://openalex.org/W2143911574"],"related_works":["https://openalex.org/W2044122268","https://openalex.org/W2376028644","https://openalex.org/W2102933388","https://openalex.org/W1994179998","https://openalex.org/W2052198094","https://openalex.org/W2070475173","https://openalex.org/W2036121598","https://openalex.org/W4389672975","https://openalex.org/W1939610338","https://openalex.org/W1965232212"],"abstract_inverted_index":{"At":[0],"65":[1],"nm":[2],"and":[3,17,57,97],"below,":[4],"parametric":[5,100],"yield":[6],"loss":[7],"has":[8,39],"become":[9],"the":[10,15,29,43,58,63],"predominant":[11],"yield-limiting":[12],"factor,":[13],"making":[14],"analysis":[16],"optimization":[18],"of":[19,32,45,54,81],"electrical":[20,33],"performance":[21],"crucial":[22],"to":[23,78,94],"market":[24],"success.":[25],"Until":[26],"now,":[27],"however,":[28],"full":[30],"efficacy":[31],"design":[34,55,82,115],"for":[35],"manufacturing":[36],"(EDFM)":[37],"tools":[38,74],"been":[40],"limited":[41],"by":[42,62],"separation":[44],"detailed":[46,52],"physical":[47],"layout":[48],"information":[49],"from":[50],"both":[51],"knowledge":[53],"intent":[56],"logical":[59],"circuits":[60],"implemented":[61],"layout.":[64],"We":[65],"introduce":[66],"a":[67,88],"Logic-Driven":[68],"Layout":[69],"Framework":[70],"that":[71],"provides":[72],"EDFM":[73],"with":[75,110],"unified":[76],"access":[77],"all":[79],"types":[80],"data":[83],"(physical,":[84],"logical,":[85],"electrical)":[86],"in":[87,113],"single":[89],"environment,":[90],"enabling":[91],"circuit":[92],"designers":[93,111],"quickly":[95],"identify":[96],"debug":[98],"potential":[99],"issues,":[101],"and,":[102],"without":[103],"losing":[104],"domain":[105],"context,":[106],"share":[107],"their":[108],"findings":[109],"working":[112],"different":[114],"domains":[116],"(logic,":[117],"layout,":[118],"manufacturing,":[119],"etc.).":[120]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2015,"cited_by_count":4},{"year":2014,"cited_by_count":1}],"updated_date":"2026-03-05T09:29:38.588285","created_date":"2025-10-10T00:00:00"}