{"id":"https://openalex.org/W2093891169","doi":"https://doi.org/10.1109/icicdt.2012.6232843","title":"Energy efficient design techniques for a digital signal processor","display_name":"Energy efficient design techniques for a digital signal processor","publication_year":2012,"publication_date":"2012-05-01","ids":{"openalex":"https://openalex.org/W2093891169","doi":"https://doi.org/10.1109/icicdt.2012.6232843","mag":"2093891169"},"language":"en","primary_location":{"id":"doi:10.1109/icicdt.2012.6232843","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icicdt.2012.6232843","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE International Conference on IC Design & Technology","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5027534418","display_name":"Paul Bassett","orcid":null},"institutions":[{"id":"https://openalex.org/I4210087596","display_name":"Qualcomm (United States)","ror":"https://ror.org/002zrf773","country_code":"US","type":"company","lineage":["https://openalex.org/I4210087596"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Paul Bassett","raw_affiliation_strings":["Qualcomm, Inc., Austin, TX, USA"],"affiliations":[{"raw_affiliation_string":"Qualcomm, Inc., Austin, TX, USA","institution_ids":["https://openalex.org/I4210087596"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5088701856","display_name":"Martin Saint-Laurent","orcid":null},"institutions":[{"id":"https://openalex.org/I4210087596","display_name":"Qualcomm (United States)","ror":"https://ror.org/002zrf773","country_code":"US","type":"company","lineage":["https://openalex.org/I4210087596"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Martin Saint-Laurent","raw_affiliation_strings":["Qualcomm, Inc., Austin, TX, USA"],"affiliations":[{"raw_affiliation_string":"Qualcomm, Inc., Austin, TX, USA","institution_ids":["https://openalex.org/I4210087596"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5027534418"],"corresponding_institution_ids":["https://openalex.org/I4210087596"],"apc_list":null,"apc_paid":null,"fwci":0.7365,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.75271986,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":96,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7142054438591003},{"id":"https://openalex.org/keywords/efficient-energy-use","display_name":"Efficient energy use","score":0.6312993168830872},{"id":"https://openalex.org/keywords/frequency-scaling","display_name":"Frequency scaling","score":0.5517275333404541},{"id":"https://openalex.org/keywords/context","display_name":"Context (archaeology)","score":0.5463750958442688},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.5302355289459229},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.49018174409866333},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4642871618270874},{"id":"https://openalex.org/keywords/power-gating","display_name":"Power gating","score":0.45957040786743164},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.43401896953582764},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.42467620968818665},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4121749699115753},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.40992674231529236},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.35326433181762695},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.26775115728378296},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1969851553440094},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17434999346733093},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.16375654935836792},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.1472007930278778},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.14602041244506836},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.11222648620605469}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7142054438591003},{"id":"https://openalex.org/C2742236","wikidata":"https://www.wikidata.org/wiki/Q924713","display_name":"Efficient energy use","level":2,"score":0.6312993168830872},{"id":"https://openalex.org/C157742956","wikidata":"https://www.wikidata.org/wiki/Q3237776","display_name":"Frequency scaling","level":3,"score":0.5517275333404541},{"id":"https://openalex.org/C2779343474","wikidata":"https://www.wikidata.org/wiki/Q3109175","display_name":"Context (archaeology)","level":2,"score":0.5463750958442688},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.5302355289459229},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.49018174409866333},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4642871618270874},{"id":"https://openalex.org/C2780700455","wikidata":"https://www.wikidata.org/wiki/Q7236515","display_name":"Power gating","level":4,"score":0.45957040786743164},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.43401896953582764},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.42467620968818665},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4121749699115753},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.40992674231529236},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.35326433181762695},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.26775115728378296},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1969851553440094},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17434999346733093},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.16375654935836792},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.1472007930278778},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.14602041244506836},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.11222648620605469},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icicdt.2012.6232843","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icicdt.2012.6232843","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE International Conference on IC Design & Technology","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8899999856948853,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2061180121","https://openalex.org/W2546524276","https://openalex.org/W2152979262","https://openalex.org/W4226239708","https://openalex.org/W2005728592","https://openalex.org/W3127845477","https://openalex.org/W2113774150","https://openalex.org/W229101532","https://openalex.org/W2938543345","https://openalex.org/W2153087216"],"abstract_inverted_index":{"Power":[0],"is":[1,23],"often":[2],"cited":[3],"as":[4,31],"a":[5,17,69,75,97],"key":[6],"design":[7,21,30,42,72,83,110],"metric":[8],"for":[9,13,128],"IC":[10],"designs.":[11],"However,":[12],"many":[14],"integrated":[15,135],"solutions":[16],"better":[18],"measure":[19],"of":[20,28,52,68,78,82,96],"quality":[22],"the":[24,29,49,66,79,92],"overall":[25,93],"energy":[26,39,94],"efficiency":[27,95],"low":[32,55],"power":[33,120,136],"does":[34],"not":[35],"always":[36],"imply":[37],"high":[38,53,60],"efficiency.":[40,61],"Many":[41],"tradeoffs":[43],"must":[44],"be":[45,87],"made":[46],"to":[47,73,89],"balance":[48],"often-conflicting":[50],"goals":[51],"performance,":[54],"power,":[56],"small":[57,76],"area":[58],"and":[59,101,107,131],"This":[62],"paper":[63],"will":[64],"use":[65],"context":[67],"DSP":[70],"core":[71],"examine":[74],"subset":[77],"full":[80],"range":[81],"techniques":[84],"that":[85],"can":[86],"leveraged":[88],"directly":[90],"impact":[91],"design:":[98],"clock":[99,103],"gating":[100],"structured":[102],"trees,":[104],"pulse":[105],"latches":[106],"other":[108],"multi-bit":[109],"structures,":[111],"8T":[112],"vs":[113,119],"6T":[114],"SRAM":[115],"arrays,":[116],"low-voltage":[117],"retention":[118],"collapse,":[121],"aggressive":[122],"process-variation-aware":[123],"frequency/voltage":[124],"scaling":[125],"with":[126],"support":[127],"both":[129],"run-fast-and-sleep":[130],"just-in-time":[132],"execution":[133],"modes,":[134],"management":[137],"solutions.":[138]},"counts_by_year":[{"year":2017,"cited_by_count":3},{"year":2014,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}