{"id":"https://openalex.org/W2000983471","doi":"https://doi.org/10.1109/ices.2014.7008729","title":"Multiobjective genetic algorithm for routability-driven circuit clustering on FPGAs","display_name":"Multiobjective genetic algorithm for routability-driven circuit clustering on FPGAs","publication_year":2014,"publication_date":"2014-12-01","ids":{"openalex":"https://openalex.org/W2000983471","doi":"https://doi.org/10.1109/ices.2014.7008729","mag":"2000983471"},"language":"en","primary_location":{"id":"doi:10.1109/ices.2014.7008729","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ices.2014.7008729","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE International Conference on Evolvable Systems","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5002438548","display_name":"Yuan Wang","orcid":"https://orcid.org/0000-0002-4951-4286"},"institutions":[{"id":"https://openalex.org/I52099693","display_name":"University of York","ror":"https://ror.org/04m01e293","country_code":"GB","type":"education","lineage":["https://openalex.org/I52099693"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Yuan Wang","raw_affiliation_strings":["Department of Electronics, University of York, York, UK","[Intelligent Systems Group, Department of Electronics, University of York, Heslington, YO10 5DD, UK]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics, University of York, York, UK","institution_ids":["https://openalex.org/I52099693"]},{"raw_affiliation_string":"[Intelligent Systems Group, Department of Electronics, University of York, Heslington, YO10 5DD, UK]","institution_ids":["https://openalex.org/I52099693"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034601593","display_name":"Simon J. Bale","orcid":"https://orcid.org/0000-0002-3361-5648"},"institutions":[{"id":"https://openalex.org/I52099693","display_name":"University of York","ror":"https://ror.org/04m01e293","country_code":"GB","type":"education","lineage":["https://openalex.org/I52099693"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Simon J. Bale","raw_affiliation_strings":["Department of Electronics, University of York, York, UK","[Intelligent Systems Group, Department of Electronics, University of York, Heslington, YO10 5DD, UK]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics, University of York, York, UK","institution_ids":["https://openalex.org/I52099693"]},{"raw_affiliation_string":"[Intelligent Systems Group, Department of Electronics, University of York, Heslington, YO10 5DD, UK]","institution_ids":["https://openalex.org/I52099693"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5017600718","display_name":"James Alfred Walker","orcid":"https://orcid.org/0000-0003-2174-7173"},"institutions":[{"id":"https://openalex.org/I52099693","display_name":"University of York","ror":"https://ror.org/04m01e293","country_code":"GB","type":"education","lineage":["https://openalex.org/I52099693"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"James Alfred Walker","raw_affiliation_strings":["Department of Electronics, University of York, York, UK","[Intelligent Systems Group, Department of Electronics, University of York, Heslington, YO10 5DD, UK]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics, University of York, York, UK","institution_ids":["https://openalex.org/I52099693"]},{"raw_affiliation_string":"[Intelligent Systems Group, Department of Electronics, University of York, Heslington, YO10 5DD, UK]","institution_ids":["https://openalex.org/I52099693"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5056241158","display_name":"Martin A. Trefzer","orcid":"https://orcid.org/0000-0002-6196-6832"},"institutions":[{"id":"https://openalex.org/I52099693","display_name":"University of York","ror":"https://ror.org/04m01e293","country_code":"GB","type":"education","lineage":["https://openalex.org/I52099693"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Martin A. Trefzer","raw_affiliation_strings":["Department of Electronics, University of York, York, UK","[Intelligent Systems Group, Department of Electronics, University of York, Heslington, YO10 5DD, UK]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics, University of York, York, UK","institution_ids":["https://openalex.org/I52099693"]},{"raw_affiliation_string":"[Intelligent Systems Group, Department of Electronics, University of York, Heslington, YO10 5DD, UK]","institution_ids":["https://openalex.org/I52099693"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5048789717","display_name":"Andy M. Tyrrell","orcid":"https://orcid.org/0000-0002-8533-2404"},"institutions":[{"id":"https://openalex.org/I52099693","display_name":"University of York","ror":"https://ror.org/04m01e293","country_code":"GB","type":"education","lineage":["https://openalex.org/I52099693"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Andy M. Tyrrell","raw_affiliation_strings":["Department of Electronics, University of York, York, UK","[Intelligent Systems Group, Department of Electronics, University of York, Heslington, YO10 5DD, UK]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics, University of York, York, UK","institution_ids":["https://openalex.org/I52099693"]},{"raw_affiliation_string":"[Intelligent Systems Group, Department of Electronics, University of York, Heslington, YO10 5DD, UK]","institution_ids":["https://openalex.org/I52099693"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I52099693"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"109","last_page":"116"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11975","display_name":"Evolutionary Algorithms and Applications","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7678139805793762},{"id":"https://openalex.org/keywords/cluster-analysis","display_name":"Cluster analysis","score":0.7075207233428955},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6836210489273071},{"id":"https://openalex.org/keywords/genetic-algorithm","display_name":"Genetic algorithm","score":0.6718230247497559},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5704329609870911},{"id":"https://openalex.org/keywords/algorithm-design","display_name":"Algorithm design","score":0.4367597699165344},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.38047701120376587},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3418315649032593},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2914576530456543},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.14681285619735718}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7678139805793762},{"id":"https://openalex.org/C73555534","wikidata":"https://www.wikidata.org/wiki/Q622825","display_name":"Cluster analysis","level":2,"score":0.7075207233428955},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6836210489273071},{"id":"https://openalex.org/C8880873","wikidata":"https://www.wikidata.org/wiki/Q187787","display_name":"Genetic algorithm","level":2,"score":0.6718230247497559},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5704329609870911},{"id":"https://openalex.org/C106516650","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm design","level":2,"score":0.4367597699165344},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.38047701120376587},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3418315649032593},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2914576530456543},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.14681285619735718},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ices.2014.7008729","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ices.2014.7008729","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE International Conference on Evolvable Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G439553668","display_name":null,"funder_award_id":"EP/I005838/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"}],"funders":[{"id":"https://openalex.org/F4320334627","display_name":"Engineering and Physical Sciences Research Council","ror":"https://ror.org/0439y7842"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":31,"referenced_works":["https://openalex.org/W124656286","https://openalex.org/W1497256448","https://openalex.org/W1523051745","https://openalex.org/W1575333164","https://openalex.org/W1612556207","https://openalex.org/W1649575244","https://openalex.org/W1905847227","https://openalex.org/W1912576130","https://openalex.org/W2002641171","https://openalex.org/W2029031086","https://openalex.org/W2045726766","https://openalex.org/W2095431940","https://openalex.org/W2109220922","https://openalex.org/W2111756578","https://openalex.org/W2113645429","https://openalex.org/W2116661285","https://openalex.org/W2124537194","https://openalex.org/W2125763038","https://openalex.org/W2125899728","https://openalex.org/W2126105956","https://openalex.org/W2137454730","https://openalex.org/W2139637699","https://openalex.org/W2150281391","https://openalex.org/W2152150600","https://openalex.org/W2261054240","https://openalex.org/W3011460294","https://openalex.org/W4241806018","https://openalex.org/W4255959021","https://openalex.org/W6605085967","https://openalex.org/W6636658889","https://openalex.org/W6662167024"],"related_works":["https://openalex.org/W2111241003","https://openalex.org/W2355315220","https://openalex.org/W4200391368","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506","https://openalex.org/W2799429316","https://openalex.org/W2161836120","https://openalex.org/W4385353603","https://openalex.org/W2946917459"],"abstract_inverted_index":{"This":[0],"paper":[1,145],"presents":[2],"a":[3,19,100,120],"novel":[4],"routability-driven":[5,161],"circuit":[6,103],"clustering":[7,104],"(packing)":[8],"technique,":[9],"DBPack,":[10],"to":[11,57,71,76,94,158],"improve":[12,147],"function":[13],"packing":[14,25,56,149,162],"on":[15,107],"FPGAs.":[16],"We":[17],"address":[18],"number":[20,36,46,121],"of":[21,26,37,47,55,63,85,122,151],"challenges":[22],"when":[23,81,156],"optimising":[24],"generic":[27],"FPGA":[28],"architectures,":[29],"which":[30],"are":[31,130],"input":[32,40],"bandwidth":[33],"constraints":[34,60],"(the":[35],"unique":[38,48],"cluster":[39,68],"signals":[41,49],"is":[42,117],"greater":[43],"than":[44],"the":[45,67,123,140,144,159],"available":[50],"from":[51],"routing":[52],"channel),":[53],"density":[54,150],"satisfy":[58],"area":[59],"and":[61,153,167],"minimisation":[62],"exposed":[64],"nets":[65],"outside":[66],"in":[69,133,143],"order":[70,75],"facilitate":[72],"routability.":[73],"In":[74],"achieve":[77],"optimal":[78],"trade-off":[79],"solutions":[80],"mapping":[82],"for":[83],"groups":[84],"Basic":[86],"Logic":[87],"Elements":[88],"(BLEs)":[89],"into":[90],"clusters":[91,152],"with":[92],"regard":[93],"multiple":[95],"objectives,":[96],"we":[97],"have":[98],"developed":[99],"population":[101],"based":[102,106],"algorithm":[105,112],"non-dominated":[108],"sorting":[109],"multi-objective":[110],"genetic":[111],"(NSGA-II).":[113],"Our":[114],"proposed":[115,142],"method":[116],"tested":[118],"using":[119],"\u201cGolden":[124],"20\u201d":[125],"MCNC":[126],"benchmark":[127],"circuits":[128],"that":[129,139],"regularly":[131],"used":[132],"FPGA-related":[134],"literature.":[135],"The":[136],"results":[137],"show":[138],"techniques":[141],"considerably":[146],"both":[148],"their":[154],"routability":[155],"compared":[157],"state-of-art":[160],"algorithms,":[163],"including":[164],"VPack,":[165],"T-VPack":[166],"RPack.":[168]},"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}