{"id":"https://openalex.org/W2084011357","doi":"https://doi.org/10.1109/ices.2013.6613280","title":"Exploiting the reconfigurability of the PAnDA architecture to overcome physical substrate variations","display_name":"Exploiting the reconfigurability of the PAnDA architecture to overcome physical substrate variations","publication_year":2013,"publication_date":"2013-04-01","ids":{"openalex":"https://openalex.org/W2084011357","doi":"https://doi.org/10.1109/ices.2013.6613280","mag":"2084011357"},"language":"en","primary_location":{"id":"doi:10.1109/ices.2013.6613280","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ices.2013.6613280","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE International Conference on Evolvable Systems (ICES)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5017600718","display_name":"James Alfred Walker","orcid":"https://orcid.org/0000-0003-2174-7173"},"institutions":[{"id":"https://openalex.org/I52099693","display_name":"University of York","ror":"https://ror.org/04m01e293","country_code":"GB","type":"education","lineage":["https://openalex.org/I52099693"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"James Alfred Walker","raw_affiliation_strings":["Intelligent Systems Group, Department of Electronics, University of York, York, UK","Intell. Syst. Group, Univ. of York, York, UK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intelligent Systems Group, Department of Electronics, University of York, York, UK","institution_ids":["https://openalex.org/I52099693"]},{"raw_affiliation_string":"Intell. Syst. Group, Univ. of York, York, UK","institution_ids":["https://openalex.org/I52099693"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5056241158","display_name":"Martin A. Trefzer","orcid":"https://orcid.org/0000-0002-6196-6832"},"institutions":[{"id":"https://openalex.org/I52099693","display_name":"University of York","ror":"https://ror.org/04m01e293","country_code":"GB","type":"education","lineage":["https://openalex.org/I52099693"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Martin A. Trefzer","raw_affiliation_strings":["Intelligent Systems Group, Department of Electronics, University of York, York, UK","Intell. Syst. Group, Univ. of York, York, UK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intelligent Systems Group, Department of Electronics, University of York, York, UK","institution_ids":["https://openalex.org/I52099693"]},{"raw_affiliation_string":"Intell. Syst. Group, Univ. of York, York, UK","institution_ids":["https://openalex.org/I52099693"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034601593","display_name":"Simon J. Bale","orcid":"https://orcid.org/0000-0002-3361-5648"},"institutions":[{"id":"https://openalex.org/I52099693","display_name":"University of York","ror":"https://ror.org/04m01e293","country_code":"GB","type":"education","lineage":["https://openalex.org/I52099693"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Simon J. Bale","raw_affiliation_strings":["Intelligent Systems Group, Department of Electronics, University of York, York, UK","Intell. Syst. Group, Univ. of York, York, UK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intelligent Systems Group, Department of Electronics, University of York, York, UK","institution_ids":["https://openalex.org/I52099693"]},{"raw_affiliation_string":"Intell. Syst. Group, Univ. of York, York, UK","institution_ids":["https://openalex.org/I52099693"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5048789717","display_name":"Andy M. Tyrrell","orcid":"https://orcid.org/0000-0002-8533-2404"},"institutions":[{"id":"https://openalex.org/I52099693","display_name":"University of York","ror":"https://ror.org/04m01e293","country_code":"GB","type":"education","lineage":["https://openalex.org/I52099693"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Andy M. Tyrrell","raw_affiliation_strings":["Intelligent Systems Group, Department of Electronics, University of York, York, UK","Intell. Syst. Group, Univ. of York, York, UK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intelligent Systems Group, Department of Electronics, University of York, York, UK","institution_ids":["https://openalex.org/I52099693"]},{"raw_affiliation_string":"Intell. Syst. Group, Univ. of York, York, UK","institution_ids":["https://openalex.org/I52099693"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I52099693"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":"1","issue":null,"first_page":"37","last_page":"42"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/reconfigurability","display_name":"Reconfigurability","score":0.9461170434951782},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7780398726463318},{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.7620807886123657},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6370572447776794},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5560222268104553},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.522864818572998},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5070359706878662},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.4944791793823242},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.47287625074386597},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.454452782869339},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.42802608013153076},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4138340651988983},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.40577709674835205},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3865888714790344},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19150406122207642},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.18999028205871582}],"concepts":[{"id":"https://openalex.org/C2780149590","wikidata":"https://www.wikidata.org/wiki/Q7302742","display_name":"Reconfigurability","level":2,"score":0.9461170434951782},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7780398726463318},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.7620807886123657},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6370572447776794},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5560222268104553},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.522864818572998},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5070359706878662},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.4944791793823242},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.47287625074386597},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.454452782869339},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.42802608013153076},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4138340651988983},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.40577709674835205},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3865888714790344},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19150406122207642},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.18999028205871582},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ices.2013.6613280","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ices.2013.6613280","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE International Conference on Evolvable Systems (ICES)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.6000000238418579}],"awards":[{"id":"https://openalex.org/G439553668","display_name":null,"funder_award_id":"EP/I005838/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"}],"funders":[{"id":"https://openalex.org/F4320334627","display_name":"Engineering and Physical Sciences Research Council","ror":"https://ror.org/0439y7842"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W147124513","https://openalex.org/W166048442","https://openalex.org/W618131878","https://openalex.org/W1563407396","https://openalex.org/W1990245197","https://openalex.org/W2000996524","https://openalex.org/W2025516544","https://openalex.org/W2032442356","https://openalex.org/W2113003532","https://openalex.org/W2117648153","https://openalex.org/W2135047781","https://openalex.org/W2138548848","https://openalex.org/W2144306385","https://openalex.org/W2149554748","https://openalex.org/W2164951071","https://openalex.org/W2539601945","https://openalex.org/W6619313483","https://openalex.org/W6680549240"],"related_works":["https://openalex.org/W2152623100","https://openalex.org/W2096417281","https://openalex.org/W25204318","https://openalex.org/W2138895528","https://openalex.org/W2077035242","https://openalex.org/W3042643149","https://openalex.org/W2026481470","https://openalex.org/W1999203047","https://openalex.org/W3201977823","https://openalex.org/W2362203107"],"abstract_inverted_index":{"Field":[0],"programmable":[1,86],"gate":[2],"arrays":[3],"(FPGAs)":[4],"are":[5,23],"widely":[6],"used":[7],"in":[8,36,55,58,77],"applications":[9],"where":[10],"on-line":[11],"reconfigurable":[12],"signal":[13],"processing":[14],"is":[15],"required.":[16],"Speed":[17],"and":[18,72,88,153],"function":[19],"density":[20],"of":[21,42,49,74,109,117,126,134],"FPGAs":[22],"increasing":[24],"as":[25,45],"transistor":[26],"sizes":[27],"shrink":[28],"to":[29,83],"the":[30,85,110,127,132,143],"nano-scale.":[31],"As":[32],"these":[33],"transistors":[34],"reduce":[35],"size,":[37],"intrinsic":[38],"variability":[39,152],"becomes":[40],"more":[41],"a":[43,50,56,99],"problem,":[44],"every":[46],"physical":[47],"instance":[48],"design":[51],"behaves":[52],"differently,":[53],"resulting":[54],"decrease":[57],"fabrication":[59],"yield.":[60],"This":[61],"paper":[62],"describes":[63],"an":[64],"adaptive,":[65],"evolvable":[66],"architecture":[67,92],"that":[68],"allows":[69],"for":[70,102],"correction":[71],"optimisation":[73,125],"circuits":[75],"directly":[76],"hardware":[78],"using":[79],"bio-inspired":[80],"techniques.":[81],"Similar":[82],"FPGAs,":[84],"analogue":[87,112,144],"digital":[89,100],"array":[90],"(PAnDA)":[91],"introduced":[93],"here":[94],"can":[95,136,147],"be":[96,137],"reconfigured":[97],"on":[98],"level":[101,113],"circuit":[103,118],"design.":[104],"Accessing":[105],"additional":[106],"configuration":[107],"options":[108],"underlying":[111],"enables":[114,123],"continuous":[115],"adjustment":[116],"characteristics":[119],"at":[120,142],"run-time,":[121],"which":[122,146],"dynamic":[124],"mapped":[128],"design's":[129],"performance.":[130],"Moreover,":[131],"yield":[133],"devices":[135],"improved":[138],"post-fabrication":[139],"via":[140],"reconfiguration":[141],"level,":[145],"overcome":[148],"faults":[149],"caused":[150],"by":[151],"process":[154],"defects.":[155]},"counts_by_year":[{"year":2014,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
