{"id":"https://openalex.org/W4323831463","doi":"https://doi.org/10.1109/iceic57457.2023.10049962","title":"Design and Comparative analysis of 6T and 7T SRAM Cells for Improved T<sub>READ</sub> and T<sub>WRITE</sub> Noise Margins","display_name":"Design and Comparative analysis of 6T and 7T SRAM Cells for Improved T<sub>READ</sub> and T<sub>WRITE</sub> Noise Margins","publication_year":2023,"publication_date":"2023-02-05","ids":{"openalex":"https://openalex.org/W4323831463","doi":"https://doi.org/10.1109/iceic57457.2023.10049962"},"language":"en","primary_location":{"id":"doi:10.1109/iceic57457.2023.10049962","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/iceic57457.2023.10049962","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 International Conference on Electronics, Information, and Communication (ICEIC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5106228213","display_name":"P. C. Tiwari","orcid":"https://orcid.org/0000-0002-3667-3843"},"institutions":[{"id":"https://openalex.org/I36909309","display_name":"National Institute of Technology Hamirpur","ror":"https://ror.org/01nc8zs04","country_code":"IN","type":"education","lineage":["https://openalex.org/I36909309","https://openalex.org/I4210152752"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Praveen Tiwari","raw_affiliation_strings":["E&#x0026;CED,NIT Hamirpur,HP,India"],"affiliations":[{"raw_affiliation_string":"E&#x0026;CED,NIT Hamirpur,HP,India","institution_ids":["https://openalex.org/I36909309"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034785880","display_name":"Rk Jarial","orcid":null},"institutions":[{"id":"https://openalex.org/I36909309","display_name":"National Institute of Technology Hamirpur","ror":"https://ror.org/01nc8zs04","country_code":"IN","type":"education","lineage":["https://openalex.org/I36909309","https://openalex.org/I4210152752"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Rk Jarial","raw_affiliation_strings":["EED,NIT Hamirpur,HP,India","EED,NIT Hamirpur, HP, India"],"affiliations":[{"raw_affiliation_string":"EED,NIT Hamirpur,HP,India","institution_ids":["https://openalex.org/I36909309"]},{"raw_affiliation_string":"EED,NIT Hamirpur, HP, India","institution_ids":["https://openalex.org/I36909309"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101493112","display_name":"Gagnesh Kumar","orcid":null},"institutions":[{"id":"https://openalex.org/I36909309","display_name":"National Institute of Technology Hamirpur","ror":"https://ror.org/01nc8zs04","country_code":"IN","type":"education","lineage":["https://openalex.org/I36909309","https://openalex.org/I4210152752"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Gagnesh Kumar","raw_affiliation_strings":["E&#x0026;CED,NIT Hamirpur,HP,India"],"affiliations":[{"raw_affiliation_string":"E&#x0026;CED,NIT Hamirpur,HP,India","institution_ids":["https://openalex.org/I36909309"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5106228213"],"corresponding_institution_ids":["https://openalex.org/I36909309"],"apc_list":null,"apc_paid":null,"fwci":0.4016,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.5791804,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":96,"max":97},"biblio":{"volume":"10","issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.9470220804214478},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.7096713185310364},{"id":"https://openalex.org/keywords/noise","display_name":"Noise (video)","score":0.583794355392456},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.5645259022712708},{"id":"https://openalex.org/keywords/memory-cell","display_name":"Memory cell","score":0.5626346468925476},{"id":"https://openalex.org/keywords/noise-margin","display_name":"Noise margin","score":0.5339480638504028},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.518624484539032},{"id":"https://openalex.org/keywords/access-time","display_name":"Access time","score":0.5170620083808899},{"id":"https://openalex.org/keywords/random-access-memory","display_name":"Random access memory","score":0.5142776370048523},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5123904347419739},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5068019032478333},{"id":"https://openalex.org/keywords/margin","display_name":"Margin (machine learning)","score":0.4959350526332855},{"id":"https://openalex.org/keywords/universal-memory","display_name":"Universal memory","score":0.4722915291786194},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.4363335371017456},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.4154992997646332},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3777955174446106},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.37085023522377014},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.33944451808929443},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.33593887090682983},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.3307238221168518},{"id":"https://openalex.org/keywords/memory-refresh","display_name":"Memory refresh","score":0.2733423113822937},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2298966944217682},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.18122044205665588},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.163487046957016}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.9470220804214478},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.7096713185310364},{"id":"https://openalex.org/C99498987","wikidata":"https://www.wikidata.org/wiki/Q2210247","display_name":"Noise (video)","level":3,"score":0.583794355392456},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.5645259022712708},{"id":"https://openalex.org/C2776638159","wikidata":"https://www.wikidata.org/wiki/Q18343761","display_name":"Memory cell","level":4,"score":0.5626346468925476},{"id":"https://openalex.org/C179499742","wikidata":"https://www.wikidata.org/wiki/Q1324892","display_name":"Noise margin","level":4,"score":0.5339480638504028},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.518624484539032},{"id":"https://openalex.org/C194080101","wikidata":"https://www.wikidata.org/wiki/Q46306","display_name":"Access time","level":2,"score":0.5170620083808899},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.5142776370048523},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5123904347419739},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5068019032478333},{"id":"https://openalex.org/C774472","wikidata":"https://www.wikidata.org/wiki/Q6760393","display_name":"Margin (machine learning)","level":2,"score":0.4959350526332855},{"id":"https://openalex.org/C195053848","wikidata":"https://www.wikidata.org/wiki/Q7894141","display_name":"Universal memory","level":5,"score":0.4722915291786194},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.4363335371017456},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.4154992997646332},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3777955174446106},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.37085023522377014},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.33944451808929443},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.33593887090682983},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.3307238221168518},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.2733423113822937},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2298966944217682},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.18122044205665588},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.163487046957016},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.0},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iceic57457.2023.10049962","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/iceic57457.2023.10049962","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 International Conference on Electronics, Information, and Communication (ICEIC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W2542332651","https://openalex.org/W2948537294","https://openalex.org/W3084922492","https://openalex.org/W3154427249","https://openalex.org/W3199912067","https://openalex.org/W4232980720"],"related_works":["https://openalex.org/W2080843961","https://openalex.org/W2039670496","https://openalex.org/W4293261839","https://openalex.org/W2123840948","https://openalex.org/W1504951709","https://openalex.org/W2186356227","https://openalex.org/W2794240619","https://openalex.org/W1521345290","https://openalex.org/W4233433957","https://openalex.org/W1998340208"],"abstract_inverted_index":{"SRAM":[0,27,54,82,123,132],"(static":[1],"random-access":[2,19],"memory)":[3,20],"is":[4,42],"used":[5],"to":[6,24,48],"store":[7,49],"the":[8,50,94,135,141],"cache":[9],"memory":[10,74],"or":[11],"data":[12,36,51],"in":[13],"static":[14],"form.":[15],"Unlike":[16],"DRAM":[17,32,45],"(dynamic":[18],"it":[21,34],"needs":[22],"not":[23],"be":[25],"refreshed.":[26],"gives":[28],"faster":[29],"access":[30],"than":[31,130],"and":[33,80,104,110,139],"retains":[35],"bits":[37,52],"as":[38,40,73,97,140],"long":[39],"power":[41],"being":[43],"supplied.":[44],"uses":[46,55],"capacitor":[47],"whereas":[53],"latching":[56,59],"circuit(flip-flop).":[57],"The":[58],"circuit":[60],"consists":[61],"of":[62],"four":[63],"transistors":[64],"(two":[65],"CMOS":[66],"inverters":[67],"which":[68],"are":[69,108],"cross":[70],"coupled)":[71],"act":[72],"part.":[75],"This":[76],"paper":[77],"compares":[78],"6T":[79,131],"7T":[81,122],"using":[83],"Tanner":[84],"EDA":[85],"tools":[86],"on":[87],"45nm":[88],"technology.":[89],"For":[90],"both":[91],"SRAMs,":[92],"all":[93],"parameters":[95],"such":[96],"Read":[98],"noise":[99,102,106,128,145],"margin,":[100,103],"W-rite":[101],"Hold":[105],"margin":[107,129],"calculated":[109],"compared":[111],"at":[112,134],"different":[113],"cell":[114,137,142],"ratios.":[115],"In":[116],"our":[117],"simulation":[118],"we":[119],"found":[120],"that":[121],"cells":[124,133],"have":[125],"a":[126],"larger":[127],"same":[136],"ratio,":[138],"ratio":[143],"increases":[144],"margins":[146],"also":[147],"increase.":[148]},"counts_by_year":[{"year":2024,"cited_by_count":3}],"updated_date":"2025-12-24T23:09:58.560324","created_date":"2025-10-10T00:00:00"}