{"id":"https://openalex.org/W3135345224","doi":"https://doi.org/10.1109/iceic51217.2021.9369710","title":"Design and Implementation of Ternary Carry Lookahead Adder on FPGA","display_name":"Design and Implementation of Ternary Carry Lookahead Adder on FPGA","publication_year":2021,"publication_date":"2021-01-31","ids":{"openalex":"https://openalex.org/W3135345224","doi":"https://doi.org/10.1109/iceic51217.2021.9369710","mag":"3135345224"},"language":"en","primary_location":{"id":"doi:10.1109/iceic51217.2021.9369710","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iceic51217.2021.9369710","pdf_url":null,"source":{"id":"https://openalex.org/S4306498844","display_name":"2021 International Conference on Electronics, Information, and Communication (ICEIC)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 International Conference on Electronics, Information, and Communication (ICEIC)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5066873322","display_name":"Jaeyoon Park","orcid":"https://orcid.org/0000-0002-2203-2666"},"institutions":[{"id":"https://openalex.org/I94588446","display_name":"Hongik University","ror":"https://ror.org/00egdv862","country_code":"KR","type":"education","lineage":["https://openalex.org/I94588446"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Jaeyoon Park","raw_affiliation_strings":["School of Electronic & Electrical Engineering, Hongik University, Seoul, Republic of Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electronic & Electrical Engineering, Hongik University, Seoul, Republic of Korea","institution_ids":["https://openalex.org/I94588446"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100337311","display_name":"Young\u2010Min Kim","orcid":"https://orcid.org/0000-0003-3220-9004"},"institutions":[{"id":"https://openalex.org/I94588446","display_name":"Hongik University","ror":"https://ror.org/00egdv862","country_code":"KR","type":"education","lineage":["https://openalex.org/I94588446"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Youngmin Kim","raw_affiliation_strings":["School of Electronic & Electrical Engineering, Hongik University, Seoul, Republic of Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electronic & Electrical Engineering, Hongik University, Seoul, Republic of Korea","institution_ids":["https://openalex.org/I94588446"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I94588446"],"apc_list":null,"apc_paid":null,"fwci":1.221,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.72345601,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"2"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13182","display_name":"Quantum-Dot Cellular Automata","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.8163186311721802},{"id":"https://openalex.org/keywords/ternary-operation","display_name":"Ternary operation","score":0.7744947671890259},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6399718523025513},{"id":"https://openalex.org/keywords/binary-number","display_name":"Binary number","score":0.6177579164505005},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5951768755912781},{"id":"https://openalex.org/keywords/carry","display_name":"Carry (investment)","score":0.517758309841156},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.5133280158042908},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.502021074295044},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.45075199007987976},{"id":"https://openalex.org/keywords/carry-save-adder","display_name":"Carry-save adder","score":0.4107479751110077},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4008774161338806},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.35930773615837097},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.343744158744812},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.24653777480125427},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.1375928521156311}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.8163186311721802},{"id":"https://openalex.org/C64452783","wikidata":"https://www.wikidata.org/wiki/Q1524945","display_name":"Ternary operation","level":2,"score":0.7744947671890259},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6399718523025513},{"id":"https://openalex.org/C48372109","wikidata":"https://www.wikidata.org/wiki/Q3913","display_name":"Binary number","level":2,"score":0.6177579164505005},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5951768755912781},{"id":"https://openalex.org/C2776299755","wikidata":"https://www.wikidata.org/wiki/Q432449","display_name":"Carry (investment)","level":2,"score":0.517758309841156},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.5133280158042908},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.502021074295044},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.45075199007987976},{"id":"https://openalex.org/C3227080","wikidata":"https://www.wikidata.org/wiki/Q5046770","display_name":"Carry-save adder","level":4,"score":0.4107479751110077},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4008774161338806},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.35930773615837097},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.343744158744812},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.24653777480125427},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.1375928521156311},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C10138342","wikidata":"https://www.wikidata.org/wiki/Q43015","display_name":"Finance","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iceic51217.2021.9369710","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iceic51217.2021.9369710","pdf_url":null,"source":{"id":"https://openalex.org/S4306498844","display_name":"2021 International Conference on Electronics, Information, and Communication (ICEIC)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 International Conference on Electronics, Information, and Communication (ICEIC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G5038043491","display_name":null,"funder_award_id":"NRF-2020R1F1A1055251","funder_id":"https://openalex.org/F4320322120","funder_display_name":"National Research Foundation of Korea"}],"funders":[{"id":"https://openalex.org/F4320322120","display_name":"National Research Foundation of Korea","ror":"https://ror.org/013aysd81"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1992764350","https://openalex.org/W2047582595","https://openalex.org/W2169245181","https://openalex.org/W3011590926","https://openalex.org/W4254387376"],"related_works":["https://openalex.org/W2127980940","https://openalex.org/W2605666407","https://openalex.org/W2157955791","https://openalex.org/W1584617340","https://openalex.org/W2064215635","https://openalex.org/W2532181444","https://openalex.org/W986131379","https://openalex.org/W2950842282","https://openalex.org/W2183905145","https://openalex.org/W2075110663"],"abstract_inverted_index":{"Ternary":[0],"value":[1],"logic":[2,35,51,127],"(TVL)":[3],"has":[4],"advantages":[5],"over":[6],"binary":[7,94,113,126],"system,":[8],"such":[9],"as":[10],"providing":[11],"smaller":[12],"chip":[13],"area":[14],"and":[15,54,72,75,107,125],"faster":[16,103],"computation":[17],"speed.":[18],"However,":[19],"ternary":[20,34,50,64,88,100,124],"hardware":[21,30],"implementation":[22],"is":[23,36,52,68,90,102],"in":[24,56],"theoretical,":[25],"simulation":[26],"levels.":[27],"Moreover,":[28],"no":[29],"description":[31],"language":[32],"for":[33],"developed.":[37],"In":[38,115],"this":[39],"paper,":[40],"by":[41],"representing":[42],"1":[43],"trit":[44],"(trinary":[45],"digit)":[46],"with":[47,92],"2":[48],"bit,":[49],"implemented":[53,69],"analyzed":[55],"FPGA.":[57],"To":[58],"specify":[59],"the":[60,73,79],"performance":[61,85],"of":[62,78,86,118],"TVL,":[63],"carry":[65,120],"lookahead":[66],"adder":[67,121],"on":[70],"FPGA":[71],"speed":[74],"power":[76,111],"dissipation":[77],"arithmetic":[80],"unit":[81],"are":[82,128],"measured.":[83],"The":[84,96],"21-trit":[87],"CLA":[89,101],"compared":[91],"32-bit":[93],"CLA.":[95,114],"results":[97],"show":[98],"that":[99],"up":[104],"to":[105],"10.36%":[106],"consumes":[108],"13.54%":[109],"less":[110],"than":[112],"addition,":[116],"performances":[117],"ripple":[119],"using":[122],"both":[123],"simulated.":[129]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}