{"id":"https://openalex.org/W2083777724","doi":"https://doi.org/10.1109/iceei.2011.6021669","title":"An FPGA implementation of a simple lossless data compression coprocessor","display_name":"An FPGA implementation of a simple lossless data compression coprocessor","publication_year":2011,"publication_date":"2011-07-01","ids":{"openalex":"https://openalex.org/W2083777724","doi":"https://doi.org/10.1109/iceei.2011.6021669","mag":"2083777724"},"language":"en","primary_location":{"id":"doi:10.1109/iceei.2011.6021669","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iceei.2011.6021669","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2011 International Conference on Electrical Engineering and Informatics","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5040119309","display_name":"Armein Z. R. Langi","orcid":"https://orcid.org/0000-0001-9516-1461"},"institutions":[{"id":"https://openalex.org/I134635517","display_name":"Bandung Institute of Technology","ror":"https://ror.org/00apj8t60","country_code":"ID","type":"education","lineage":["https://openalex.org/I134635517"]}],"countries":["ID"],"is_corresponding":true,"raw_author_name":"Armein Z. R. Langi","raw_affiliation_strings":["DSP-RTG, Institut'Teknologi Bandung, Bandung, Indonesia","ITB Research Center on Information and Communication Technology, Institut Teknologi Bandung, JalanGaneca 10, Indonesia 40132"],"affiliations":[{"raw_affiliation_string":"DSP-RTG, Institut'Teknologi Bandung, Bandung, Indonesia","institution_ids":["https://openalex.org/I134635517"]},{"raw_affiliation_string":"ITB Research Center on Information and Communication Technology, Institut Teknologi Bandung, JalanGaneca 10, Indonesia 40132","institution_ids":["https://openalex.org/I134635517"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5040119309"],"corresponding_institution_ids":["https://openalex.org/I134635517"],"apc_list":null,"apc_paid":null,"fwci":0.5037,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.664853,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9958000183105469,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9958000183105469,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9955999851226807,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9952999949455261,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/lossless-compression","display_name":"Lossless compression","score":0.8401626348495483},{"id":"https://openalex.org/keywords/encoder","display_name":"Encoder","score":0.8386553525924683},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7985254526138306},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7234718799591064},{"id":"https://openalex.org/keywords/coprocessor","display_name":"Coprocessor","score":0.6428019404411316},{"id":"https://openalex.org/keywords/data-compression","display_name":"Data compression","score":0.5722064971923828},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5468312501907349},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.478031724691391},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.4603313207626343},{"id":"https://openalex.org/keywords/code","display_name":"Code (set theory)","score":0.4556387662887573},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4335019886493683},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.35109466314315796},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.29464036226272583}],"concepts":[{"id":"https://openalex.org/C81081738","wikidata":"https://www.wikidata.org/wiki/Q55542","display_name":"Lossless compression","level":3,"score":0.8401626348495483},{"id":"https://openalex.org/C118505674","wikidata":"https://www.wikidata.org/wiki/Q42586063","display_name":"Encoder","level":2,"score":0.8386553525924683},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7985254526138306},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7234718799591064},{"id":"https://openalex.org/C86111242","wikidata":"https://www.wikidata.org/wiki/Q859595","display_name":"Coprocessor","level":2,"score":0.6428019404411316},{"id":"https://openalex.org/C78548338","wikidata":"https://www.wikidata.org/wiki/Q2493","display_name":"Data compression","level":2,"score":0.5722064971923828},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5468312501907349},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.478031724691391},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.4603313207626343},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.4556387662887573},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4335019886493683},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.35109466314315796},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.29464036226272583},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iceei.2011.6021669","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iceei.2011.6021669","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2011 International Conference on Electrical Engineering and Informatics","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":1,"referenced_works":["https://openalex.org/W1963850047"],"related_works":["https://openalex.org/W2364622490","https://openalex.org/W2948148442","https://openalex.org/W2461250372","https://openalex.org/W2394342941","https://openalex.org/W2169853506","https://openalex.org/W2547124190","https://openalex.org/W2350586049","https://openalex.org/W2385628723","https://openalex.org/W2057878850","https://openalex.org/W2032414556"],"abstract_inverted_index":{"The":[0,40,63,87,97,114],"paper":[1],"describes":[2],"a":[3,15,77,83],"Field":[4],"Programmable":[5],"Gate":[6],"Array":[7],"(FPGA)-based":[8],"lossless":[9,60],"data":[10,34],"compression":[11,16],"coprocessor":[12],"using":[13],"implementing":[14],"method":[17],"developed":[18],"by":[19],"Rice.":[20],"We":[21],"have":[22],"implemented":[23],"the":[24],"Rice":[25,98,115],"code":[26,41],"(both":[27],"encoder":[28,64,99,139],"and":[29,65,71,94,110,127,140],"decoder)":[30],"for":[31],"8":[32],"bit/sample":[33],"on":[35,48],"an":[36,132],"FPGA":[37],"Xilinx":[38],"XC4005.":[39],"has":[42],"been":[43],"designed":[44],"to":[45,82,136],"be":[46],"optimal":[47],"1.5":[49,84],"<;":[50,52],"H":[51],"7.5":[53],"bits/sample,":[54],"that":[55],"is":[56,134],"usually":[57],"required":[58],"in":[59],"image":[61],"compression.":[62],"decoder":[66,116],"can":[67],"achieve":[68],"11.6":[69],"MHz":[70,73,79],"19.4":[72],"clock,":[74],"respectively,":[75],"where":[76],"10":[78],"clock":[80],"corresponds":[81],"Mbits/s":[85],"throughput.":[86],"XC4005":[88],"contains":[89],"combinatorial":[90],"logic":[91],"units":[92],"(CLU)":[93],"I/O":[95,112,129],"pins.":[96,113],"uses":[100,117],"30%":[101],"CLB":[102,105,108,119,122,125],"F&G,":[103,120],"15%":[104],"H,":[106,123],"16%":[107,124],"FF,":[109,126],"34%":[111,128],"31%":[118],"19%":[121],"pin.":[130],"Hence,":[131],"X4005":[133],"sufficient":[135],"implement":[137],"both":[138],"decoder.":[141]},"counts_by_year":[{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
