{"id":"https://openalex.org/W2900456139","doi":"https://doi.org/10.1109/iceee.2018.8533979","title":"Memristive Optimizer for the Assignment Task","display_name":"Memristive Optimizer for the Assignment Task","publication_year":2018,"publication_date":"2018-09-01","ids":{"openalex":"https://openalex.org/W2900456139","doi":"https://doi.org/10.1109/iceee.2018.8533979","mag":"2900456139"},"language":"en","primary_location":{"id":"doi:10.1109/iceee.2018.8533979","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iceee.2018.8533979","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 15th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5080243001","display_name":"Gerardo Marcos Tornez Xavier","orcid":"https://orcid.org/0000-0002-6823-292X"},"institutions":[{"id":"https://openalex.org/I68368234","display_name":"Center for Research and Advanced Studies of the National Polytechnic Institute","ror":"https://ror.org/009eqmr18","country_code":"MX","type":"facility","lineage":["https://openalex.org/I59361560","https://openalex.org/I68368234"]}],"countries":["MX"],"is_corresponding":true,"raw_author_name":"G.M. Tornez-Xavier","raw_affiliation_strings":["Department of Electrical Engineering, CINVESTAV-IPN, Mexico City, Mexico"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, CINVESTAV-IPN, Mexico City, Mexico","institution_ids":["https://openalex.org/I68368234"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5069617247","display_name":"L.M. Flores\u2010Nava","orcid":null},"institutions":[{"id":"https://openalex.org/I68368234","display_name":"Center for Research and Advanced Studies of the National Polytechnic Institute","ror":"https://ror.org/009eqmr18","country_code":"MX","type":"facility","lineage":["https://openalex.org/I59361560","https://openalex.org/I68368234"]}],"countries":["MX"],"is_corresponding":false,"raw_author_name":"L.M. Flores-Nava","raw_affiliation_strings":["Department of Electrical Engineering, CINVESTAV-IPN, Mexico City, Mexico"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, CINVESTAV-IPN, Mexico City, Mexico","institution_ids":["https://openalex.org/I68368234"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031433169","display_name":"F. G\u00f3mez\u2010Casta\u00f1eda","orcid":null},"institutions":[{"id":"https://openalex.org/I68368234","display_name":"Center for Research and Advanced Studies of the National Polytechnic Institute","ror":"https://ror.org/009eqmr18","country_code":"MX","type":"facility","lineage":["https://openalex.org/I59361560","https://openalex.org/I68368234"]}],"countries":["MX"],"is_corresponding":false,"raw_author_name":"F. Gomez-Castaneda","raw_affiliation_strings":["Department of Electrical Engineering, CINVESTAV-IPN, Mexico City, Mexico"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, CINVESTAV-IPN, Mexico City, Mexico","institution_ids":["https://openalex.org/I68368234"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5056077409","display_name":"J.A. Moreno\u2010Cadenas","orcid":null},"institutions":[{"id":"https://openalex.org/I68368234","display_name":"Center for Research and Advanced Studies of the National Polytechnic Institute","ror":"https://ror.org/009eqmr18","country_code":"MX","type":"facility","lineage":["https://openalex.org/I59361560","https://openalex.org/I68368234"]}],"countries":["MX"],"is_corresponding":false,"raw_author_name":"J.A. Moreno-Cadenas","raw_affiliation_strings":["Department of Electrical Engineering, CINVESTAV-IPN, Mexico City, Mexico"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, CINVESTAV-IPN, Mexico City, Mexico","institution_ids":["https://openalex.org/I68368234"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5080243001"],"corresponding_institution_ids":["https://openalex.org/I68368234"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.11727812,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"453","issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11601","display_name":"Neuroscience and Neural Engineering","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/2804","display_name":"Cellular and Molecular Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7538020014762878},{"id":"https://openalex.org/keywords/memristor","display_name":"Memristor","score":0.7254949808120728},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6738741993904114},{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.6559567451477051},{"id":"https://openalex.org/keywords/resistor","display_name":"Resistor","score":0.645672082901001},{"id":"https://openalex.org/keywords/task","display_name":"Task (project management)","score":0.6451131105422974},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4701314866542816},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4339580535888672},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.4237607419490814},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3491193652153015},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.27396517992019653},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21840810775756836},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.18048986792564392},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1262107491493225}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7538020014762878},{"id":"https://openalex.org/C150072547","wikidata":"https://www.wikidata.org/wiki/Q212923","display_name":"Memristor","level":2,"score":0.7254949808120728},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6738741993904114},{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.6559567451477051},{"id":"https://openalex.org/C137488568","wikidata":"https://www.wikidata.org/wiki/Q5321","display_name":"Resistor","level":3,"score":0.645672082901001},{"id":"https://openalex.org/C2780451532","wikidata":"https://www.wikidata.org/wiki/Q759676","display_name":"Task (project management)","level":2,"score":0.6451131105422974},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4701314866542816},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4339580535888672},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.4237607419490814},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3491193652153015},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.27396517992019653},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21840810775756836},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.18048986792564392},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1262107491493225},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iceee.2018.8533979","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iceee.2018.8533979","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 15th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1968902264","https://openalex.org/W2004782555","https://openalex.org/W2008901850","https://openalex.org/W2052918019","https://openalex.org/W2112181056","https://openalex.org/W2162651880","https://openalex.org/W4210746732"],"related_works":["https://openalex.org/W2015297467","https://openalex.org/W2105831835","https://openalex.org/W2035017065","https://openalex.org/W2094066961","https://openalex.org/W2285231005","https://openalex.org/W2323645878","https://openalex.org/W3049246456","https://openalex.org/W4241208885","https://openalex.org/W2159731583","https://openalex.org/W4242780158"],"abstract_inverted_index":{"This":[0],"work":[1,12],"shows":[2],"an":[3,33],"analog":[4],"CMOS":[5,89,99],"matrix":[6,38],"compatible":[7],"with":[8,97],"memristors,":[9],"where":[10,44],"they":[11],"as":[13,32,69,82],"dynamic":[14],"resistors.":[15],"They":[16],"are":[17,67],"also":[18],"programmed":[19],"to":[20,25,56],"initial":[21],"state":[22],"values":[23],"according":[24],"one":[26],"assignment":[27],"optimization":[28],"task,":[29],"taken":[30],"here":[31],"application":[34],"vehicle.":[35],"The":[36,52],"whole":[37],"accomplishes":[39],"a":[40,45],"parallel":[41],"competitive":[42],"computation,":[43],"winner-take-all":[46],"mechanism":[47],"is":[48,70,80],"inherent":[49],"by":[50],"architecture.":[51],"expected":[53],"complexity":[54],"due":[55],"area":[57],"in":[58],"silicon":[59],"of":[60],"this":[61],"memristive":[62],"circuit":[63],"and":[64],"its":[65,74,78],"connectivity":[66],"moderate,":[68],"evident":[71],"from":[72],"observing":[73],"electrical":[75],"diagram.":[76],"Also,":[77],"performance":[79],"acceptable":[81],"proven":[83],"via":[84],"SPICE":[85],"simulations,":[86],"using":[87],"0.5-micron":[88],"process.":[90],"Lower":[91],"processing":[92],"time":[93],"might":[94],"be":[95],"possible":[96],"latest":[98],"technologies.":[100]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}