{"id":"https://openalex.org/W2090052973","doi":"https://doi.org/10.1109/iceee.2014.6978288","title":"Characterization technique to implement self-timed cells for VLSI design blocks","display_name":"Characterization technique to implement self-timed cells for VLSI design blocks","publication_year":2014,"publication_date":"2014-09-01","ids":{"openalex":"https://openalex.org/W2090052973","doi":"https://doi.org/10.1109/iceee.2014.6978288","mag":"2090052973"},"language":"en","primary_location":{"id":"doi:10.1109/iceee.2014.6978288","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iceee.2014.6978288","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 11th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5060102766","display_name":"Susana Ortega Cisneros","orcid":"https://orcid.org/0000-0001-6646-1529"},"institutions":[{"id":"https://openalex.org/I68368234","display_name":"Centro de Investigaci\u00f3n y de Estudios Avanzados del Instituto Polit\u00e9cnico Nacional","ror":"https://ror.org/009eqmr18","country_code":"MX","type":"facility","lineage":["https://openalex.org/I59361560","https://openalex.org/I68368234"]}],"countries":["MX"],"is_corresponding":false,"raw_author_name":"Susana Ortega Cisneros","raw_affiliation_strings":["CINVESTAV, Centro de Investigaciones y de Estudios Avanzados del IPN, Guadalajara, M\u00e9xico","CINVESTAV, Centro de Investigaciones y de Estudios Avanzados del, IPN, Guadalajara, M\u00e9xico"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"CINVESTAV, Centro de Investigaciones y de Estudios Avanzados del IPN, Guadalajara, M\u00e9xico","institution_ids":["https://openalex.org/I68368234"]},{"raw_affiliation_string":"CINVESTAV, Centro de Investigaciones y de Estudios Avanzados del, IPN, Guadalajara, M\u00e9xico","institution_ids":["https://openalex.org/I68368234"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060104328","display_name":"Juan Jos\u00e9 Raygoza Panduro","orcid":"https://orcid.org/0000-0002-8567-4981"},"institutions":[{"id":"https://openalex.org/I193181351","display_name":"Universidad de Guadalajara","ror":"https://ror.org/043xj7k26","country_code":"MX","type":"education","lineage":["https://openalex.org/I193181351"]}],"countries":["MX"],"is_corresponding":false,"raw_author_name":"Juan Jose Raygoza Panduro","raw_affiliation_strings":["Dept. de Electron., Universidad de Guadalajara, Guadalajara, Jalisco, MX","Departamento de Electr\u00f3nica, CUCEI, Universidad de Guadalajara, Guadalajara, M\u00e9xico"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. de Electron., Universidad de Guadalajara, Guadalajara, Jalisco, MX","institution_ids":["https://openalex.org/I193181351"]},{"raw_affiliation_string":"Departamento de Electr\u00f3nica, CUCEI, Universidad de Guadalajara, Guadalajara, M\u00e9xico","institution_ids":["https://openalex.org/I193181351"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111860440","display_name":"Jos\u00e9 Roberto Reyes Bar\u00f3n","orcid":null},"institutions":[{"id":"https://openalex.org/I193181351","display_name":"Universidad de Guadalajara","ror":"https://ror.org/043xj7k26","country_code":"MX","type":"education","lineage":["https://openalex.org/I193181351"]}],"countries":["MX"],"is_corresponding":false,"raw_author_name":"Jose Roberto Reyes Baron","raw_affiliation_strings":["Departamento de Electr\u00f3nica, Universidad de Guadalajara, Guadalajara, Jalisco, MX","Departamento de Electr\u00f3nica, CUCEI, Universidad de Guadalajara, Guadalajara, M\u00e9xico"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Departamento de Electr\u00f3nica, Universidad de Guadalajara, Guadalajara, Jalisco, MX","institution_ids":["https://openalex.org/I193181351"]},{"raw_affiliation_string":"Departamento de Electr\u00f3nica, CUCEI, Universidad de Guadalajara, Guadalajara, M\u00e9xico","institution_ids":["https://openalex.org/I193181351"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5049620872","display_name":"Brice\u00f1o Aranda","orcid":null},"institutions":[{"id":"https://openalex.org/I193181351","display_name":"Universidad de Guadalajara","ror":"https://ror.org/043xj7k26","country_code":"MX","type":"education","lineage":["https://openalex.org/I193181351"]}],"countries":["MX"],"is_corresponding":false,"raw_author_name":"B. Daniel Tonali Aranda","raw_affiliation_strings":["Departamento de Electr\u00f3nica, Universidad de Guadalajara, Guadalajara, Jalisco, MX","Departamento de Electr\u00f3nica, CUCEI, Universidad de Guadalajara, Guadalajara, M\u00e9xico"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Departamento de Electr\u00f3nica, Universidad de Guadalajara, Guadalajara, Jalisco, MX","institution_ids":["https://openalex.org/I193181351"]},{"raw_affiliation_string":"Departamento de Electr\u00f3nica, CUCEI, Universidad de Guadalajara, Guadalajara, M\u00e9xico","institution_ids":["https://openalex.org/I193181351"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5055248137","display_name":"Z. Antonio Casillas","orcid":null},"institutions":[{"id":"https://openalex.org/I193181351","display_name":"Universidad de Guadalajara","ror":"https://ror.org/043xj7k26","country_code":"MX","type":"education","lineage":["https://openalex.org/I193181351"]}],"countries":["MX"],"is_corresponding":false,"raw_author_name":"Z. Antonio Casillas","raw_affiliation_strings":["Departamento de Electr\u00f3nica CUCEI, Universidad de Guadalajara, Guadalajara, M\u00e9xico","Departamento de Electr\u00f3nica, CUCEI, Universidad de Guadalajara, Guadalajara, M\u00e9xico"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Departamento de Electr\u00f3nica CUCEI, Universidad de Guadalajara, Guadalajara, M\u00e9xico","institution_ids":["https://openalex.org/I193181351"]},{"raw_affiliation_string":"Departamento de Electr\u00f3nica, CUCEI, Universidad de Guadalajara, Guadalajara, M\u00e9xico","institution_ids":["https://openalex.org/I193181351"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.12730625,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7404350638389587},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.7326475381851196},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.6895142793655396},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.63835608959198},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.6200652718544006},{"id":"https://openalex.org/keywords/characterization","display_name":"Characterization (materials science)","score":0.5458822250366211},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.47594666481018066},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.45967796444892883},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.43395593762397766},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3884970545768738},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.37927332520484924},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3739584684371948},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.35592466592788696},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.3367752432823181},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3343374729156494},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.15704113245010376},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.13572779297828674},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1271149218082428}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7404350638389587},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.7326475381851196},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.6895142793655396},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.63835608959198},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.6200652718544006},{"id":"https://openalex.org/C2780841128","wikidata":"https://www.wikidata.org/wiki/Q5073781","display_name":"Characterization (materials science)","level":2,"score":0.5458822250366211},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.47594666481018066},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.45967796444892883},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.43395593762397766},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3884970545768738},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.37927332520484924},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3739584684371948},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.35592466592788696},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.3367752432823181},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3343374729156494},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.15704113245010376},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.13572779297828674},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1271149218082428},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.0},{"id":"https://openalex.org/C171250308","wikidata":"https://www.wikidata.org/wiki/Q11468","display_name":"Nanotechnology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iceee.2014.6978288","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iceee.2014.6978288","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 11th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320321739","display_name":"Consejo Nacional de Ciencia y Tecnolog\u00eda","ror":"https://ror.org/059ex5q34"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W2141045120","https://openalex.org/W2172098243","https://openalex.org/W4231067439"],"related_works":["https://openalex.org/W2355622827","https://openalex.org/W2072989701","https://openalex.org/W1738647919","https://openalex.org/W3000179092","https://openalex.org/W1986774039","https://openalex.org/W2050511294","https://openalex.org/W2118321428","https://openalex.org/W2063172373","https://openalex.org/W2045408571","https://openalex.org/W2019084430"],"abstract_inverted_index":{"In":[0],"this":[1,18,42,148],"article,":[2],"a":[3,48,72,189],"methodology":[4],"to":[5,52,110,114],"obtain":[6],"the":[7,10,32,36,44,53,56,78,85,88,94,102,106,111,116,120,129,133,150,155,159,180,185,193],"characterization":[8,60,90],"of":[9,46,55,68,87,93,100,105,122,128,132,195],"standard":[11,69],"cell":[12],"library":[13,19,96,187],"called":[14],"SXLIB":[15],"is":[16,20,28,108,178],"presented,":[17],"available":[21],"within":[22],"Alliance":[23,145],"tools.":[24,146],"The":[25,98],"later":[26],"proposal":[27],"developed":[29],"based":[30],"on":[31],"spreading":[33,103],"analysis":[34],"that":[35,75,143,154],"signal":[37],"has":[38],"throughout":[39],"each":[40],"cell,":[41],"with":[43,65],"objective":[45],"obtaining":[47],"delay":[49],"time":[50,104,113,168],"according":[51],"technology":[54,74],"manufacture's":[57],"receiver.":[58],"This":[59,125],"technique":[61],"can":[62],"be":[63],"used":[64,81],"any":[66],"set":[67],"cells,":[70],"for":[71],"manufacturing":[73],"differs":[76],"by":[77,82],"default":[79],"one":[80,127],"Alliance,":[83],"then,":[84],"results":[86,182],"new":[89],"are":[91],"presented":[92],"specified":[95],"SXLIB.":[97],"importance":[99],"knowing":[101],"signal,":[107],"due":[109],"required":[112],"include":[115],"necessary":[117],"delays":[118],"in":[119,139,162,167,192],"design":[121,134,194],"self-timed":[123,196],"structures.":[124,197],"is,":[126],"key":[130,190],"phases":[131],"and":[135,170],"synthesis":[136],"process,":[137],"expressed":[138],"structural":[140],"language":[141],"VHDL":[142],"generates":[144],"Throughout":[147],"phase,":[149],"designer":[151],"will":[152],"prove":[153],"IC":[156],"works":[157],"under":[158],"desired":[160],"behavior,":[161],"form":[163],"(logic":[164],"operation)":[165],"as":[166],"(maximum":[169],"minimum":[171],"delays,":[172],"maximum":[173],"work":[174],"frequencies,":[175],"etc.).":[176],"That":[177],"because":[179],"obtained":[181],"from":[183],"using":[184],"characterized":[186],"represent":[188],"point":[191]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}