{"id":"https://openalex.org/W1972882568","doi":"https://doi.org/10.1109/iceee.2012.6421136","title":"4-Bit Arithmetic Logic Unit (ALU) based on Neuron MOS Transistors","display_name":"4-Bit Arithmetic Logic Unit (ALU) based on Neuron MOS Transistors","publication_year":2012,"publication_date":"2012-09-01","ids":{"openalex":"https://openalex.org/W1972882568","doi":"https://doi.org/10.1109/iceee.2012.6421136","mag":"1972882568"},"language":"en","primary_location":{"id":"doi:10.1109/iceee.2012.6421136","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iceee.2012.6421136","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 9th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5054286444","display_name":"E. A. Cortes-Barron","orcid":null},"institutions":[{"id":"https://openalex.org/I68368234","display_name":"Centro de Investigaci\u00f3n y de Estudios Avanzados del Instituto Polit\u00e9cnico Nacional","ror":"https://ror.org/009eqmr18","country_code":"MX","type":"facility","lineage":["https://openalex.org/I59361560","https://openalex.org/I68368234"]}],"countries":["MX"],"is_corresponding":false,"raw_author_name":"E. A. Cort\u00e9s-Barr\u00f3n","raw_affiliation_strings":["Electrical Engineering Department, Solid State Electronics Section, CINVESTAV-IPN, Mexico D.F., México","Electrical Engineering Department, Solid State Electronics Section, CINVESTAV-IPN, Mexico D.F., M\u00e9xico"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical Engineering Department, Solid State Electronics Section, CINVESTAV-IPN, Mexico D.F., México","institution_ids":["https://openalex.org/I68368234"]},{"raw_affiliation_string":"Electrical Engineering Department, Solid State Electronics Section, CINVESTAV-IPN, Mexico D.F., M\u00e9xico","institution_ids":["https://openalex.org/I68368234"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5012359830","display_name":"M. A. Reyes\u2013Barranca","orcid":null},"institutions":[{"id":"https://openalex.org/I68368234","display_name":"Centro de Investigaci\u00f3n y de Estudios Avanzados del Instituto Polit\u00e9cnico Nacional","ror":"https://ror.org/009eqmr18","country_code":"MX","type":"facility","lineage":["https://openalex.org/I59361560","https://openalex.org/I68368234"]}],"countries":["MX"],"is_corresponding":false,"raw_author_name":"M. A. Reyes-Barranca","raw_affiliation_strings":["Electrical Engineering Department, Solid State Electronics Section, CINVESTAV-IPN, Mexico D.F., México","Electrical Engineering Department, Solid State Electronics Section, CINVESTAV-IPN, Mexico D.F., M\u00e9xico"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical Engineering Department, Solid State Electronics Section, CINVESTAV-IPN, Mexico D.F., México","institution_ids":["https://openalex.org/I68368234"]},{"raw_affiliation_string":"Electrical Engineering Department, Solid State Electronics Section, CINVESTAV-IPN, Mexico D.F., M\u00e9xico","institution_ids":["https://openalex.org/I68368234"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5069617247","display_name":"L.M. Flores\u2010Nava","orcid":null},"institutions":[{"id":"https://openalex.org/I68368234","display_name":"Centro de Investigaci\u00f3n y de Estudios Avanzados del Instituto Polit\u00e9cnico Nacional","ror":"https://ror.org/009eqmr18","country_code":"MX","type":"facility","lineage":["https://openalex.org/I59361560","https://openalex.org/I68368234"]}],"countries":["MX"],"is_corresponding":false,"raw_author_name":"L. M. Flores-Nava","raw_affiliation_strings":["Electrical Engineering Department, Solid State Electronics Section, CINVESTAV-IPN, Mexico D.F., México","Electrical Engineering Department, Solid State Electronics Section, CINVESTAV-IPN, Mexico D.F., M\u00e9xico"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical Engineering Department, Solid State Electronics Section, CINVESTAV-IPN, Mexico D.F., México","institution_ids":["https://openalex.org/I68368234"]},{"raw_affiliation_string":"Electrical Engineering Department, Solid State Electronics Section, CINVESTAV-IPN, Mexico D.F., M\u00e9xico","institution_ids":["https://openalex.org/I68368234"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5062525003","display_name":"Alejandro Medina Santiago","orcid":"https://orcid.org/0000-0003-4468-9850"},"institutions":[{"id":"https://openalex.org/I3084848766","display_name":"Tuxtla Gutierrez Institute of Technology","ror":"https://ror.org/05tdek150","country_code":"MX","type":"education","lineage":["https://openalex.org/I3084848766"]}],"countries":["MX"],"is_corresponding":false,"raw_author_name":"A. Medina-Santiago","raw_affiliation_strings":["Instituto Tecnológico de Tuxtla Gutiérrez, Chiapas, México","Instituto Tecnol\u00f3gico de Tuxtla Guti\u00e9rrez, Chiapas, M\u00e9xico"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Instituto Tecnológico de Tuxtla Gutiérrez, Chiapas, México","institution_ids":["https://openalex.org/I3084848766"]},{"raw_affiliation_string":"Instituto Tecnol\u00f3gico de Tuxtla Guti\u00e9rrez, Chiapas, M\u00e9xico","institution_ids":["https://openalex.org/I3084848766"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.07107489,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10320","display_name":"Neural Networks and Applications","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10320","display_name":"Neural Networks and Applications","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9958999752998352,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/arithmetic-logic-unit","display_name":"Arithmetic logic unit","score":0.8609006404876709},{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.7774990797042847},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6496046781539917},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6150047779083252},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5777285099029541},{"id":"https://openalex.org/keywords/and-or-invert","display_name":"AND-OR-Invert","score":0.5463204979896545},{"id":"https://openalex.org/keywords/nor-gate","display_name":"NOR gate","score":0.5085731744766235},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.4871930480003357},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.47186797857284546},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.44238194823265076},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.44192489981651306},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.44122976064682007},{"id":"https://openalex.org/keywords/gate-array","display_name":"Gate array","score":0.4243188202381134},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.37725451588630676},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.3692333698272705},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.2896828055381775},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.2887008786201477},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2644895017147064},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.18499761819839478},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17570072412490845},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1634570062160492}],"concepts":[{"id":"https://openalex.org/C100276221","wikidata":"https://www.wikidata.org/wiki/Q192903","display_name":"Arithmetic logic unit","level":2,"score":0.8609006404876709},{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.7774990797042847},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6496046781539917},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6150047779083252},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5777285099029541},{"id":"https://openalex.org/C130126468","wikidata":"https://www.wikidata.org/wiki/Q4652943","display_name":"AND-OR-Invert","level":5,"score":0.5463204979896545},{"id":"https://openalex.org/C126445297","wikidata":"https://www.wikidata.org/wiki/Q8065380","display_name":"NOR gate","level":4,"score":0.5085731744766235},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.4871930480003357},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.47186797857284546},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.44238194823265076},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.44192489981651306},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.44122976064682007},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.4243188202381134},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.37725451588630676},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.3692333698272705},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.2896828055381775},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.2887008786201477},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2644895017147064},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.18499761819839478},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17570072412490845},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1634570062160492}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iceee.2012.6421136","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iceee.2012.6421136","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 9th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.6399999856948853}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W1983051814","https://openalex.org/W1993352835","https://openalex.org/W2008047718","https://openalex.org/W2095722715"],"related_works":["https://openalex.org/W188762367","https://openalex.org/W4361799621","https://openalex.org/W2565020286","https://openalex.org/W1017999001","https://openalex.org/W4252993849","https://openalex.org/W2109857948","https://openalex.org/W2151687972","https://openalex.org/W2279974209","https://openalex.org/W4295177619","https://openalex.org/W2765435638"],"abstract_inverted_index":{"A":[0],"methodology":[1],"is":[2,23,50,78],"proposed":[3,178],"for":[4,43,125,170],"the":[5,21,26,44,54,136,141,145,153,177],"design":[6,179],"of":[7,20,62,128,135,144,176,185],"a":[8,32,82,108,116,126,162,189],"4-Bit":[9,119],"Arithmetic":[10],"Logic":[11],"Unit":[12],"(ALU)":[13],"based":[14,24],"on":[15,25,107],"Soft-Hardware-Logic":[16],"(SHL).":[17],"The":[18],"core":[19],"implementation":[22],"device":[27],"known":[28],"as":[29],"neu-MOS":[30],"(\u03bd-MOS),":[31],"floating-gate":[33],"MOS":[34],"transistor":[35],"with":[36,72,182,188],"more":[37],"than":[38],"one":[39],"control":[40],"gate":[41,143],"used":[42],"digital":[45,74],"signal":[46],"processing.":[47],"This":[48],"configuration":[49],"reconfigurable":[51],"modifying":[52],"only":[53],"external":[55],"voltages":[56],"applied":[57],"to":[58,158],"an":[59],"intermediate":[60],"stage":[61],"programmable":[63],"CMOS":[64,164],"inverters,":[65],"without":[66],"any":[67],"circuitry":[68],"change,":[69],"in":[70],"contrast":[71],"conventional":[73],"implementations.":[75],"Here":[76],"it":[77],"demonstrated":[79],"that":[80],"using":[81,99],"universal":[83],"circuit,":[84],"basic":[85,118],"Boolean":[86],"functions":[87,132],"like":[88],"AND,":[89],"NAND,":[90],"OR,":[91],"NOR,":[92],"Exclusive-OR":[93],"and":[94,123,130,155,193],"Exclusive-NOR":[95],"can":[96,149],"be":[97,150],"configured":[98,187],"Multiple-Input":[100],"Floating-Gate":[101],"(MIFG)":[102],"Transistors":[103],"or":[104],"neu-MOS.":[105,146],"Based":[106],"graphical":[109],"method":[110],"called":[111],"Floating-gate":[112],"Potential":[113],"Diagram":[114],"(FPD),":[115],"very":[117],"ALU":[120,196],"was":[121],"designed":[122],"simulated":[124],"couple":[127],"arithmetic":[129],"logic":[131],"taking":[133],"advantage":[134],"weighted":[137],"sum":[138],"performed":[139],"at":[140],"floating":[142],"Weighted":[147],"inputs":[148],"obtained":[151,173],"from":[152,174],"FPD":[154],"then":[156],"converted":[157],"effective":[159],"capacitances":[160],"choosing":[161],"given":[163],"technology,":[165,169],"OnSemi's":[166],"0.5":[167],"\u03bcm":[168],"instance.":[171],"Results":[172],"simulations":[175],"are":[180],"compared":[181],"experimental":[183],"results":[184],"ALUs":[186],"FPGA":[190],"evaluation":[191],"kit":[192],"Motorola's":[194],"MC14581B":[195],"chip.":[197]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":2}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}