{"id":"https://openalex.org/W4417169760","doi":"https://doi.org/10.1109/icecs66544.2025.11270800","title":"A Memoryless Stream Processing Architecture for Energy-Efficient Signal Processing","display_name":"A Memoryless Stream Processing Architecture for Energy-Efficient Signal Processing","publication_year":2025,"publication_date":"2025-11-17","ids":{"openalex":"https://openalex.org/W4417169760","doi":"https://doi.org/10.1109/icecs66544.2025.11270800"},"language":null,"primary_location":{"id":"doi:10.1109/icecs66544.2025.11270800","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs66544.2025.11270800","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 32nd IEEE International Conference on Electronics, Circuits and Systems (ICECS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5120734647","display_name":"Clara Ciocan","orcid":null},"institutions":[{"id":"https://openalex.org/I4210128565","display_name":"CEA Paris-Saclay","ror":"https://ror.org/03n15ch10","country_code":"FR","type":"government","lineage":["https://openalex.org/I2738703131","https://openalex.org/I277688954","https://openalex.org/I4210128565"]},{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"funder","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I2738703131","display_name":"Commissariat \u00e0 l'\u00c9nergie Atomique et aux \u00c9nergies Alternatives","ror":"https://ror.org/00jjx8s55","country_code":"FR","type":"funder","lineage":["https://openalex.org/I2738703131"]},{"id":"https://openalex.org/I277688954","display_name":"Universit\u00e9 Paris-Saclay","ror":"https://ror.org/03xjwb503","country_code":"FR","type":"education","lineage":["https://openalex.org/I277688954"]}],"countries":["FR"],"is_corresponding":true,"raw_author_name":"Clara Ciocan","raw_affiliation_strings":["Université Paris-Saclay,CEA, CNRS, SPEC,France"],"affiliations":[{"raw_affiliation_string":"Université Paris-Saclay,CEA, CNRS, SPEC,France","institution_ids":["https://openalex.org/I277688954","https://openalex.org/I2738703131","https://openalex.org/I4210128565","https://openalex.org/I1294671590"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5075714992","display_name":"Anthony Kolar","orcid":"https://orcid.org/0000-0002-4041-1723"},"institutions":[{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"funder","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I4210107720","display_name":"CentraleSup\u00e9lec","ror":"https://ror.org/019tcpt25","country_code":"FR","type":"facility","lineage":["https://openalex.org/I277688954","https://openalex.org/I4210107720"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Anthony Kolar","raw_affiliation_strings":["Université Paris-Saclay,CentraleSupélec, CNRS, GEEPS,France"],"affiliations":[{"raw_affiliation_string":"Université Paris-Saclay,CentraleSupélec, CNRS, GEEPS,France","institution_ids":["https://openalex.org/I4210107720","https://openalex.org/I1294671590"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5022587191","display_name":"Mathieu Th\u00e9venin","orcid":"https://orcid.org/0000-0002-9962-1135"},"institutions":[{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"funder","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I2738703131","display_name":"Commissariat \u00e0 l'\u00c9nergie Atomique et aux \u00c9nergies Alternatives","ror":"https://ror.org/00jjx8s55","country_code":"FR","type":"funder","lineage":["https://openalex.org/I2738703131"]},{"id":"https://openalex.org/I4210128565","display_name":"CEA Paris-Saclay","ror":"https://ror.org/03n15ch10","country_code":"FR","type":"government","lineage":["https://openalex.org/I2738703131","https://openalex.org/I277688954","https://openalex.org/I4210128565"]},{"id":"https://openalex.org/I277688954","display_name":"Universit\u00e9 Paris-Saclay","ror":"https://ror.org/03xjwb503","country_code":"FR","type":"education","lineage":["https://openalex.org/I277688954"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Mathieu Thevenin","raw_affiliation_strings":["Université Paris-Saclay,CEA, CNRS, SPEC,France"],"affiliations":[{"raw_affiliation_string":"Université Paris-Saclay,CEA, CNRS, SPEC,France","institution_ids":["https://openalex.org/I277688954","https://openalex.org/I2738703131","https://openalex.org/I4210128565","https://openalex.org/I1294671590"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5120734647"],"corresponding_institution_ids":["https://openalex.org/I1294671590","https://openalex.org/I2738703131","https://openalex.org/I277688954","https://openalex.org/I4210128565"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.45543397,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.7883999943733215,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.7883999943733215,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.15950000286102295,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.0066999997943639755,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/stream-processing","display_name":"Stream processing","score":0.7217000126838684},{"id":"https://openalex.org/keywords/signal-processing","display_name":"Signal processing","score":0.5472999811172485},{"id":"https://openalex.org/keywords/simd","display_name":"SIMD","score":0.5306000113487244},{"id":"https://openalex.org/keywords/memory-footprint","display_name":"Memory footprint","score":0.453000009059906},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.44510000944137573},{"id":"https://openalex.org/keywords/footprint","display_name":"Footprint","score":0.3869999945163727},{"id":"https://openalex.org/keywords/bitstream","display_name":"Bitstream","score":0.3580000102519989},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.3578000068664551}],"concepts":[{"id":"https://openalex.org/C107027933","wikidata":"https://www.wikidata.org/wiki/Q2006448","display_name":"Stream processing","level":2,"score":0.7217000126838684},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7174000144004822},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.5472999811172485},{"id":"https://openalex.org/C150552126","wikidata":"https://www.wikidata.org/wiki/Q339387","display_name":"SIMD","level":2,"score":0.5306000113487244},{"id":"https://openalex.org/C74912251","wikidata":"https://www.wikidata.org/wiki/Q6815727","display_name":"Memory footprint","level":2,"score":0.453000009059906},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.44510000944137573},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.415800005197525},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.41029998660087585},{"id":"https://openalex.org/C132943942","wikidata":"https://www.wikidata.org/wiki/Q2562511","display_name":"Footprint","level":2,"score":0.3869999945163727},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3619999885559082},{"id":"https://openalex.org/C136695289","wikidata":"https://www.wikidata.org/wiki/Q415568","display_name":"Bitstream","level":3,"score":0.3580000102519989},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.3578000068664551},{"id":"https://openalex.org/C2778484313","wikidata":"https://www.wikidata.org/wiki/Q1172540","display_name":"Data stream","level":2,"score":0.34389999508857727},{"id":"https://openalex.org/C106515295","wikidata":"https://www.wikidata.org/wiki/Q26806595","display_name":"Parallel processing","level":2,"score":0.3310000002384186},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3253999948501587},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.32190001010894775},{"id":"https://openalex.org/C98025372","wikidata":"https://www.wikidata.org/wiki/Q477538","display_name":"Systems architecture","level":3,"score":0.31349998712539673},{"id":"https://openalex.org/C18762648","wikidata":"https://www.wikidata.org/wiki/Q42213","display_name":"Work (physics)","level":2,"score":0.28859999775886536},{"id":"https://openalex.org/C12725497","wikidata":"https://www.wikidata.org/wiki/Q810247","display_name":"Baseline (sea)","level":2,"score":0.28850001096725464},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.28029999136924744},{"id":"https://openalex.org/C125411270","wikidata":"https://www.wikidata.org/wiki/Q18653","display_name":"Encoding (memory)","level":2,"score":0.2676999866962433},{"id":"https://openalex.org/C55526617","wikidata":"https://www.wikidata.org/wiki/Q719375","display_name":"Operand","level":2,"score":0.26649999618530273},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.2630999982357025},{"id":"https://openalex.org/C168167062","wikidata":"https://www.wikidata.org/wiki/Q1117970","display_name":"Component (thermodynamics)","level":2,"score":0.2549000084400177},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.25360000133514404},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.25189998745918274}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icecs66544.2025.11270800","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs66544.2025.11270800","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 32nd IEEE International Conference on Electronics, Circuits and Systems (ICECS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W220440441","https://openalex.org/W1977850862","https://openalex.org/W1999085092","https://openalex.org/W2108824541","https://openalex.org/W2148356449","https://openalex.org/W2886489698","https://openalex.org/W4285207860","https://openalex.org/W4308536756"],"related_works":[],"abstract_inverted_index":{"This":[0,80],"paper":[1],"introduces":[2],"a":[3,17,22,27,49],"memoryless":[4,92],"stream":[5,24,34],"processing":[6],"architecture":[7],"designed":[8],"for":[9,71],"energy-efficient":[10],"signal":[11],"processing.":[12],"The":[13],"proposed":[14],"design":[15],"integrates":[16],"modified":[18],"RISC-V":[19,56],"core":[20],"with":[21],"centralized":[23],"manager":[25],"and":[26,63,77,87],"delayed":[28],"SIMD":[29],"execution":[30],"model.":[31],"Unlike":[32],"conventional":[33],"processors,":[35],"our":[36],"approach":[37],"eliminates":[38],"the":[39,61,66,84,91],"need":[40],"of":[41,65,90],"memory":[42],"while":[43],"retaining":[44],"programmability.":[45],"Post-layout":[46],"results":[47],"demonstrate":[48],"reduced":[50],"silicon":[51],"footprint":[52],"compared":[53],"to":[54],"baseline":[55],"implementations.":[57],"Preliminary":[58],"experiments":[59],"confirm":[60],"feasibility":[62],"compactness":[64],"architecture,":[67],"highlighting":[68],"its":[69],"suitability":[70],"constrained":[72],"domains":[73],"such":[74],"as":[75],"biomedical":[76],"cryogenic":[78],"systems.":[79],"work":[81],"highlights":[82],"both":[83],"architectural":[85],"benefits":[86],"current":[88],"limitations":[89],"paradigm.":[93]},"counts_by_year":[],"updated_date":"2026-03-07T16:01:11.037858","created_date":"2025-12-09T00:00:00"}