{"id":"https://openalex.org/W4417169250","doi":"https://doi.org/10.1109/icecs66544.2025.11270722","title":"Resource Efficient Direct Digital Frequency Synthesizer Architecture on FPGA","display_name":"Resource Efficient Direct Digital Frequency Synthesizer Architecture on FPGA","publication_year":2025,"publication_date":"2025-11-17","ids":{"openalex":"https://openalex.org/W4417169250","doi":"https://doi.org/10.1109/icecs66544.2025.11270722"},"language":"en","primary_location":{"id":"doi:10.1109/icecs66544.2025.11270722","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs66544.2025.11270722","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 32nd IEEE International Conference on Electronics, Circuits and Systems (ICECS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5007426935","display_name":"Kalle I. Palom\u00e4ki","orcid":null},"institutions":[{"id":"https://openalex.org/I4210133110","display_name":"Tampere University","ror":null,"country_code":"FI","type":null,"lineage":["https://openalex.org/I4210133110"]}],"countries":["FI"],"is_corresponding":true,"raw_author_name":"Kalle I. Palom\u00e4ki","raw_affiliation_strings":["Tampere University,Wireless Research Center,Tampere,Finland"],"affiliations":[{"raw_affiliation_string":"Tampere University,Wireless Research Center,Tampere,Finland","institution_ids":["https://openalex.org/I4210133110"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5035297149","display_name":"Jari Nurmi","orcid":"https://orcid.org/0000-0003-2169-4606"},"institutions":[{"id":"https://openalex.org/I4210133110","display_name":"Tampere University","ror":null,"country_code":"FI","type":null,"lineage":["https://openalex.org/I4210133110"]}],"countries":["FI"],"is_corresponding":false,"raw_author_name":"Jari Nurmi","raw_affiliation_strings":["Tampere University,Wireless Research Center,Tampere,Finland"],"affiliations":[{"raw_affiliation_string":"Tampere University,Wireless Research Center,Tampere,Finland","institution_ids":["https://openalex.org/I4210133110"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5007426935"],"corresponding_institution_ids":["https://openalex.org/I4210133110"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.40046905,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9599999785423279,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9599999785423279,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.02250000089406967,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.007499999832361937,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/direct-digital-synthesizer","display_name":"Direct digital synthesizer","score":0.8895000219345093},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7340999841690063},{"id":"https://openalex.org/keywords/spurious-relationship","display_name":"Spurious relationship","score":0.6850000023841858},{"id":"https://openalex.org/keywords/frequency-synthesizer","display_name":"Frequency synthesizer","score":0.5892000198364258},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.4156999886035919},{"id":"https://openalex.org/keywords/digital-signal","display_name":"Digital signal","score":0.4140999913215637},{"id":"https://openalex.org/keywords/gate-array","display_name":"Gate array","score":0.39750000834465027},{"id":"https://openalex.org/keywords/frequency-multiplier","display_name":"Frequency multiplier","score":0.3928000032901764},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.3652999997138977}],"concepts":[{"id":"https://openalex.org/C166089067","wikidata":"https://www.wikidata.org/wiki/Q1227465","display_name":"Direct digital synthesizer","level":5,"score":0.8895000219345093},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7340999841690063},{"id":"https://openalex.org/C97256817","wikidata":"https://www.wikidata.org/wiki/Q1462316","display_name":"Spurious relationship","level":2,"score":0.6850000023841858},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6146000027656555},{"id":"https://openalex.org/C182099602","wikidata":"https://www.wikidata.org/wiki/Q2660678","display_name":"Frequency synthesizer","level":4,"score":0.5892000198364258},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5728999972343445},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.45980000495910645},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4156999886035919},{"id":"https://openalex.org/C52773712","wikidata":"https://www.wikidata.org/wiki/Q175022","display_name":"Digital signal","level":3,"score":0.4140999913215637},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.39750000834465027},{"id":"https://openalex.org/C146002875","wikidata":"https://www.wikidata.org/wiki/Q1074289","display_name":"Frequency multiplier","level":3,"score":0.3928000032901764},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.3652999997138977},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.35760000348091125},{"id":"https://openalex.org/C119293636","wikidata":"https://www.wikidata.org/wiki/Q657480","display_name":"Spurious-free dynamic range","level":3,"score":0.33869999647140503},{"id":"https://openalex.org/C89836824","wikidata":"https://www.wikidata.org/wiki/Q160710","display_name":"Read-only memory","level":2,"score":0.3327000141143799},{"id":"https://openalex.org/C36390408","wikidata":"https://www.wikidata.org/wiki/Q1163067","display_name":"Digital filter","level":3,"score":0.3303000032901764},{"id":"https://openalex.org/C206345919","wikidata":"https://www.wikidata.org/wiki/Q20380951","display_name":"Resource (disambiguation)","level":2,"score":0.33000001311302185},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.3285999894142151},{"id":"https://openalex.org/C204323151","wikidata":"https://www.wikidata.org/wiki/Q905424","display_name":"Range (aeronautics)","level":2,"score":0.3224000036716461},{"id":"https://openalex.org/C180205008","wikidata":"https://www.wikidata.org/wiki/Q159190","display_name":"Amplitude","level":2,"score":0.3192000091075897},{"id":"https://openalex.org/C11930861","wikidata":"https://www.wikidata.org/wiki/Q181417","display_name":"Frequency modulation","level":3,"score":0.30000001192092896},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2996000051498413},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.28949999809265137},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.2818000018596649},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.28060001134872437},{"id":"https://openalex.org/C62869609","wikidata":"https://www.wikidata.org/wiki/Q28137","display_name":"Quadrature (astronomy)","level":2,"score":0.2770000100135803},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.27219998836517334},{"id":"https://openalex.org/C87133666","wikidata":"https://www.wikidata.org/wiki/Q1161699","display_name":"Dynamic range","level":2,"score":0.2696000039577484},{"id":"https://openalex.org/C2779879419","wikidata":"https://www.wikidata.org/wiki/Q210863","display_name":"Digital-to-analog converter","level":3,"score":0.26440000534057617},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.2556999921798706},{"id":"https://openalex.org/C161611012","wikidata":"https://www.wikidata.org/wiki/Q106370","display_name":"Digital signal processor","level":3,"score":0.25380000472068787},{"id":"https://openalex.org/C143724316","wikidata":"https://www.wikidata.org/wiki/Q312468","display_name":"Series (stratigraphy)","level":2,"score":0.25040000677108765}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/icecs66544.2025.11270722","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs66544.2025.11270722","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 32nd IEEE International Conference on Electronics, Circuits and Systems (ICECS)","raw_type":"proceedings-article"},{"id":"pmh:oai:trepo.tuni.fi:10024/233664","is_oa":false,"landing_page_url":"https://trepo.tuni.fi/handle/10024/233664","pdf_url":null,"source":{"id":"https://openalex.org/S7407055260","display_name":"Trepo - Institutional Repository of Tampere University","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"conference"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1669074376","https://openalex.org/W2111698733","https://openalex.org/W2141492992","https://openalex.org/W2170675900","https://openalex.org/W3008837131","https://openalex.org/W3016137691","https://openalex.org/W3094214451","https://openalex.org/W3128461779","https://openalex.org/W4256164501","https://openalex.org/W4360585175","https://openalex.org/W4402989293","https://openalex.org/W4404971006","https://openalex.org/W4406520973"],"related_works":[],"abstract_inverted_index":{"Direct":[0,51],"Digital":[1,52],"Frequency":[2,53],"Synthesizer":[3,54],"(DDFS)":[4,55],"is":[5,68],"a":[6,46,71],"device":[7],"that":[8,57],"creates":[9],"digital":[10],"samples":[11],"of":[12,32,100],"analog":[13],"signals.":[14],"The":[15,66,85],"DDFS":[16],"designs":[17],"commonly":[18],"use":[19],"memory":[20,34],"to":[21],"store":[22],"these":[23],"samples.":[24],"However,":[25],"as":[26],"the":[27,30,33,63,94],"accuracy":[28],"increases,":[29],"size":[31],"grows":[35],"both":[36],"in":[37,62],"width":[38],"and":[39,82,91],"depth.":[40],"In":[41],"this":[42],"paper,":[43],"we":[44],"present":[45],"resource":[47],"efficient,":[48],"12-bit":[49],"quadrature":[50],"architecture":[56],"applies":[58],"Taylor":[59],"series":[60],"approximation":[61],"amplitude":[64],"computation.":[65],"design":[67,86],"implemented":[69],"on":[70],"field":[72],"programmable":[73],"gate":[74],"array":[75],"(FPGA),":[76],"where":[77],"it":[78,92],"consumes":[79],"266":[80],"LUTs":[81],"236":[83],"Flip-Flops.":[84],"has":[87],"high":[88],"signal":[89],"quality,":[90],"reaches":[93],"spurious":[95],"free":[96],"dynamic":[97],"range":[98],"(SFDR)":[99],"-80.8":[101],"dBc.":[102]},"counts_by_year":[],"updated_date":"2026-03-09T08:58:05.943551","created_date":"2025-12-09T00:00:00"}