{"id":"https://openalex.org/W4417170035","doi":"https://doi.org/10.1109/icecs66544.2025.11270716","title":"A Power-Efficient Analog Integrated K-means Classifier Architecture for Brain Stroke Prediction","display_name":"A Power-Efficient Analog Integrated K-means Classifier Architecture for Brain Stroke Prediction","publication_year":2025,"publication_date":"2025-11-17","ids":{"openalex":"https://openalex.org/W4417170035","doi":"https://doi.org/10.1109/icecs66544.2025.11270716"},"language":null,"primary_location":{"id":"doi:10.1109/icecs66544.2025.11270716","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs66544.2025.11270716","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 32nd IEEE International Conference on Electronics, Circuits and Systems (ICECS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5024524906","display_name":"Vassilis Alimisis","orcid":"https://orcid.org/0000-0002-2090-1493"},"institutions":[{"id":"https://openalex.org/I174458059","display_name":"National Technical University of Athens","ror":"https://ror.org/03cx6bg69","country_code":"GR","type":"education","lineage":["https://openalex.org/I174458059"]}],"countries":["GR"],"is_corresponding":true,"raw_author_name":"Vassilis Alimisis","raw_affiliation_strings":["National Technical University of Athens,Department of Electrical and Computer Engineering,Athens,Greece,15780"],"affiliations":[{"raw_affiliation_string":"National Technical University of Athens,Department of Electrical and Computer Engineering,Athens,Greece,15780","institution_ids":["https://openalex.org/I174458059"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5106330378","display_name":"Konstantinos Cheliotis","orcid":null},"institutions":[{"id":"https://openalex.org/I174458059","display_name":"National Technical University of Athens","ror":"https://ror.org/03cx6bg69","country_code":"GR","type":"education","lineage":["https://openalex.org/I174458059"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Konstantinos Cheliotis","raw_affiliation_strings":["National Technical University of Athens,Department of Electrical and Computer Engineering,Athens,Greece,15780"],"affiliations":[{"raw_affiliation_string":"National Technical University of Athens,Department of Electrical and Computer Engineering,Athens,Greece,15780","institution_ids":["https://openalex.org/I174458059"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5119040011","display_name":"Anna Mylona","orcid":null},"institutions":[{"id":"https://openalex.org/I174458059","display_name":"National Technical University of Athens","ror":"https://ror.org/03cx6bg69","country_code":"GR","type":"education","lineage":["https://openalex.org/I174458059"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Anna Mylona","raw_affiliation_strings":["National Technical University of Athens,Department of Electrical and Computer Engineering,Athens,Greece,15780"],"affiliations":[{"raw_affiliation_string":"National Technical University of Athens,Department of Electrical and Computer Engineering,Athens,Greece,15780","institution_ids":["https://openalex.org/I174458059"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5040477973","display_name":"Vasileios Moustakas","orcid":null},"institutions":[{"id":"https://openalex.org/I174458059","display_name":"National Technical University of Athens","ror":"https://ror.org/03cx6bg69","country_code":"GR","type":"education","lineage":["https://openalex.org/I174458059"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Vasileios Moustakas","raw_affiliation_strings":["National Technical University of Athens,Department of Electrical and Computer Engineering,Athens,Greece,15780"],"affiliations":[{"raw_affiliation_string":"National Technical University of Athens,Department of Electrical and Computer Engineering,Athens,Greece,15780","institution_ids":["https://openalex.org/I174458059"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5013213336","display_name":"Paul P. Sotiriadis","orcid":"https://orcid.org/0000-0001-6030-4645"},"institutions":[{"id":"https://openalex.org/I174458059","display_name":"National Technical University of Athens","ror":"https://ror.org/03cx6bg69","country_code":"GR","type":"education","lineage":["https://openalex.org/I174458059"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Paul P. Sotiriadis","raw_affiliation_strings":["National Technical University of Athens,Department of Electrical and Computer Engineering,Athens,Greece,15780"],"affiliations":[{"raw_affiliation_string":"National Technical University of Athens,Department of Electrical and Computer Engineering,Athens,Greece,15780","institution_ids":["https://openalex.org/I174458059"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5024524906"],"corresponding_institution_ids":["https://openalex.org/I174458059"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.41678103,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10429","display_name":"EEG and Brain-Computer Interfaces","score":0.6535999774932861,"subfield":{"id":"https://openalex.org/subfields/2805","display_name":"Cognitive Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}},"topics":[{"id":"https://openalex.org/T10429","display_name":"EEG and Brain-Computer Interfaces","score":0.6535999774932861,"subfield":{"id":"https://openalex.org/subfields/2805","display_name":"Cognitive Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.07370000332593918,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.046799998730421066,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/classifier","display_name":"Classifier (UML)","score":0.6061999797821045},{"id":"https://openalex.org/keywords/robustness","display_name":"Robustness (evolution)","score":0.5530999898910522},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5260000228881836},{"id":"https://openalex.org/keywords/artificial-neural-network","display_name":"Artificial neural network","score":0.5112000107765198},{"id":"https://openalex.org/keywords/subtractor","display_name":"Subtractor","score":0.46950000524520874},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.459199994802475}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6640999913215637},{"id":"https://openalex.org/C95623464","wikidata":"https://www.wikidata.org/wiki/Q1096149","display_name":"Classifier (UML)","level":2,"score":0.6061999797821045},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.5795000195503235},{"id":"https://openalex.org/C63479239","wikidata":"https://www.wikidata.org/wiki/Q7353546","display_name":"Robustness (evolution)","level":3,"score":0.5530999898910522},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5260000228881836},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.5112000107765198},{"id":"https://openalex.org/C187805909","wikidata":"https://www.wikidata.org/wiki/Q1142401","display_name":"Subtractor","level":4,"score":0.46950000524520874},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.459199994802475},{"id":"https://openalex.org/C153180895","wikidata":"https://www.wikidata.org/wiki/Q7148389","display_name":"Pattern recognition (psychology)","level":2,"score":0.37389999628067017},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.31450000405311584},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.3109999895095825},{"id":"https://openalex.org/C51632099","wikidata":"https://www.wikidata.org/wiki/Q3985153","display_name":"Training set","level":2,"score":0.28299999237060547},{"id":"https://openalex.org/C19499675","wikidata":"https://www.wikidata.org/wiki/Q232207","display_name":"Monte Carlo method","level":2,"score":0.2502000033855438}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icecs66544.2025.11270716","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs66544.2025.11270716","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 32nd IEEE International Conference on Electronics, Circuits and Systems (ICECS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":36,"referenced_works":["https://openalex.org/W1512629291","https://openalex.org/W2003522442","https://openalex.org/W2014617390","https://openalex.org/W2041908012","https://openalex.org/W2086447159","https://openalex.org/W2106314901","https://openalex.org/W2120461003","https://openalex.org/W2120695048","https://openalex.org/W2123597802","https://openalex.org/W2160197181","https://openalex.org/W2495671179","https://openalex.org/W2511413133","https://openalex.org/W2534814983","https://openalex.org/W2753095659","https://openalex.org/W2884395782","https://openalex.org/W2896122000","https://openalex.org/W2897597575","https://openalex.org/W2910166072","https://openalex.org/W2920878483","https://openalex.org/W3008180137","https://openalex.org/W3012277039","https://openalex.org/W3045032114","https://openalex.org/W3046111136","https://openalex.org/W3217195399","https://openalex.org/W4251751018","https://openalex.org/W4255289481","https://openalex.org/W4284705734","https://openalex.org/W4306916468","https://openalex.org/W4367320920","https://openalex.org/W4384067832","https://openalex.org/W4386332664","https://openalex.org/W4399154284","https://openalex.org/W4400229734","https://openalex.org/W4401284396","https://openalex.org/W4402039234","https://openalex.org/W4412012162"],"related_works":[],"abstract_inverted_index":{"This":[0,114],"work":[1],"presents":[2],"a":[3,36,47,79],"low-power":[4],"analog":[5,18,31,33],"integrated":[6],"K-means":[7],"classifier":[8,56],"for":[9,121],"real-time":[10,119],"brain":[11,80],"stroke":[12,81],"prediction.":[13],"The":[14,55,101],"design":[15],"utilizes":[16],"sub-threshold":[17],"circuitry;":[19],"including":[20],"current-mode":[21],"subtractor":[22],"circuits,":[23,25],"squarer":[24],"current":[26],"mirrors,":[27],"an":[28,85],"argmin":[29],"operator,":[30],"switches,":[32],"memory,":[34],"and":[35,46,73,99,107],"low-pass":[37],"filter.":[38],"It":[39,65],"achieves":[40],"ultra-low":[41],"power":[42],"consumption":[43],"of":[44,50,89],"793nW":[45],"classification":[48,87,120],"speed":[49],"560K":[51],"inferences":[52],"per":[53],"second.":[54],"is":[57,103],"implemented":[58],"using":[59],"the":[60,96,112],"TSMC":[61],"90nm":[62],"CMOS":[63],"process.":[64],"consistently":[66],"demonstrates":[67],"good":[68],"performance":[69],"across":[70],"process,":[71],"voltage,":[72],"temperature":[74],"variations":[75],"when":[76],"evaluated":[77],"on":[78],"prediction":[82],"dataset,":[83],"achieving":[84],"average":[86],"accuracy":[88],"93.95%.":[90],"Monte":[91],"Carlo":[92],"analysis":[93],"further":[94],"confirms":[95],"design\u2019s":[97],"robustness":[98],"reliability.":[100],"model":[102],"trained":[104],"in":[105,111],"software":[106],"compared":[108],"with":[109],"works":[110],"literature.":[113],"approach":[115],"enables":[116],"efficient,":[117],"edge-based,":[118],"biomedical":[122],"applications.":[123]},"counts_by_year":[],"updated_date":"2026-03-07T16:01:11.037858","created_date":"2025-12-09T00:00:00"}
