{"id":"https://openalex.org/W4417169812","doi":"https://doi.org/10.1109/icecs66544.2025.11270685","title":"100MS/s Time-Mode PWM Signal Processing Building Blocks","display_name":"100MS/s Time-Mode PWM Signal Processing Building Blocks","publication_year":2025,"publication_date":"2025-11-17","ids":{"openalex":"https://openalex.org/W4417169812","doi":"https://doi.org/10.1109/icecs66544.2025.11270685"},"language":null,"primary_location":{"id":"doi:10.1109/icecs66544.2025.11270685","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs66544.2025.11270685","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 32nd IEEE International Conference on Electronics, Circuits and Systems (ICECS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5030791026","display_name":"Konstantinos P. Pagkalos","orcid":"https://orcid.org/0000-0001-6360-0036"},"institutions":[{"id":"https://openalex.org/I174878644","display_name":"University of Patras","ror":"https://ror.org/017wvtq80","country_code":"GR","type":"education","lineage":["https://openalex.org/I174878644"]}],"countries":["GR"],"is_corresponding":true,"raw_author_name":"Konstantinos P. Pagkalos","raw_affiliation_strings":["University of Patras,Electronics Laboratory,Physics Dept.,Rio Achaia,Greece,26504"],"affiliations":[{"raw_affiliation_string":"University of Patras,Electronics Laboratory,Physics Dept.,Rio Achaia,Greece,26504","institution_ids":["https://openalex.org/I174878644"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5120734668","display_name":"Aikaterini I. Chronopoulou","orcid":null},"institutions":[{"id":"https://openalex.org/I174878644","display_name":"University of Patras","ror":"https://ror.org/017wvtq80","country_code":"GR","type":"education","lineage":["https://openalex.org/I174878644"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Aikaterini I. Chronopoulou","raw_affiliation_strings":["University of Patras,Electronics Laboratory,Physics Dept.,Rio Achaia,Greece,26504"],"affiliations":[{"raw_affiliation_string":"University of Patras,Electronics Laboratory,Physics Dept.,Rio Achaia,Greece,26504","institution_ids":["https://openalex.org/I174878644"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5069238230","display_name":"S. Vlassis","orcid":"https://orcid.org/0000-0003-2687-0285"},"institutions":[{"id":"https://openalex.org/I174878644","display_name":"University of Patras","ror":"https://ror.org/017wvtq80","country_code":"GR","type":"education","lineage":["https://openalex.org/I174878644"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Spyridon Vlassis","raw_affiliation_strings":["University of Patras,Electronics Laboratory,Physics Dept.,Rio Achaia,Greece,26504"],"affiliations":[{"raw_affiliation_string":"University of Patras,Electronics Laboratory,Physics Dept.,Rio Achaia,Greece,26504","institution_ids":["https://openalex.org/I174878644"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5030791026"],"corresponding_institution_ids":["https://openalex.org/I174878644"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.42421336,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.4526999890804291,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.4526999890804291,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.351500004529953,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.11760000139474869,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.6614000201225281},{"id":"https://openalex.org/keywords/pulse-width-modulation","display_name":"Pulse-width modulation","score":0.5293999910354614},{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.5062000155448914},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.4587000012397766},{"id":"https://openalex.org/keywords/calibration","display_name":"Calibration","score":0.4253000020980835},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.38580000400543213},{"id":"https://openalex.org/keywords/sampling","display_name":"Sampling (signal processing)","score":0.37450000643730164},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.35920000076293945}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.6614000201225281},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.558899998664856},{"id":"https://openalex.org/C92746544","wikidata":"https://www.wikidata.org/wiki/Q585184","display_name":"Pulse-width modulation","level":3,"score":0.5293999910354614},{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.5062000155448914},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.46129998564720154},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.4587000012397766},{"id":"https://openalex.org/C165838908","wikidata":"https://www.wikidata.org/wiki/Q736777","display_name":"Calibration","level":2,"score":0.4253000020980835},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.38580000400543213},{"id":"https://openalex.org/C140779682","wikidata":"https://www.wikidata.org/wiki/Q210868","display_name":"Sampling (signal processing)","level":3,"score":0.37450000643730164},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.35920000076293945},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.35370001196861267},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.3427000045776367},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.335099995136261},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.32989999651908875},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.3091999888420105},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.28600001335144043},{"id":"https://openalex.org/C72475854","wikidata":"https://www.wikidata.org/wiki/Q477049","display_name":"Booth's multiplication algorithm","level":4,"score":0.28299999237060547},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.27720001339912415},{"id":"https://openalex.org/C2780586882","wikidata":"https://www.wikidata.org/wiki/Q7520643","display_name":"Simple (philosophy)","level":2,"score":0.26989999413490295},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.2694000005722046},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.26089999079704285},{"id":"https://openalex.org/C204323151","wikidata":"https://www.wikidata.org/wiki/Q905424","display_name":"Range (aeronautics)","level":2,"score":0.2531000077724457},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.25270000100135803}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icecs66544.2025.11270685","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs66544.2025.11270685","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 32nd IEEE International Conference on Electronics, Circuits and Systems (ICECS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W2134713152","https://openalex.org/W2790070598","https://openalex.org/W2981766591","https://openalex.org/W4206121983","https://openalex.org/W4220710636","https://openalex.org/W4311591648","https://openalex.org/W4402508194","https://openalex.org/W4404520522","https://openalex.org/W4407693971"],"related_works":[],"abstract_inverted_index":{"In":[0,59],"this":[1],"paper,":[2],"a":[3,18,61,82],"full":[4],"set":[5],"of":[6,17,38,47,70,85,100,116],"sampled":[7],"data":[8],"time-mode":[9],"PWM":[10,97],"building":[11],"blocks":[12,32,41],"is":[13,64,104],"proposed.":[14],"The":[15,36,95],"implementations":[16],"delay":[19,102],"tap,":[20],"time":[21,24,110],"adder":[22],"and":[23,51],"multiplier":[25],"are":[26,29,42,74],"presented":[27],"which":[28,54],"the":[30,39,43,49,67,101,117],"fundamental":[31],"for":[33],"FIR/IIR":[34],"filters.":[35],"benefits":[37],"proposed":[40,65],"high":[44],"sampling":[45],"rate":[46],"100MS/s,":[48],"simple":[50],"modular":[52],"structure":[53],"comes":[55],"with":[56,107],"lower":[57],"consumption.":[58,94],"addition,":[60],"calibration":[62,114],"concept":[63],"using":[66,76],"bulk":[68],"terminal":[69],"devices.":[71],"All":[72],"circuits":[73],"designed":[75],"65":[77],"nm":[78],"TSMC":[79],"process":[80],"under":[81],"supply":[83],"voltage":[84],"1.2":[86],"V,":[87],"performing":[88],"at":[89],"around":[90],"0.6":[91],"\u03bcW/MHz/tap":[92],"average":[93],"full-scale":[96],"input":[98,118],"range":[99],"tap":[103],"2.5":[105],"ns":[106],"worst":[108],"case":[109],"registration":[111],"error":[112],"after":[113],"0.17%":[115],"range.":[119]},"counts_by_year":[],"updated_date":"2026-03-07T16:01:11.037858","created_date":"2025-12-09T00:00:00"}