{"id":"https://openalex.org/W4417170375","doi":"https://doi.org/10.1109/icecs66544.2025.11270671","title":"A High Linearity 5-GHz 4-Bit Sub 1ps-DNL Phase Interpolator","display_name":"A High Linearity 5-GHz 4-Bit Sub 1ps-DNL Phase Interpolator","publication_year":2025,"publication_date":"2025-11-17","ids":{"openalex":"https://openalex.org/W4417170375","doi":"https://doi.org/10.1109/icecs66544.2025.11270671"},"language":null,"primary_location":{"id":"doi:10.1109/icecs66544.2025.11270671","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs66544.2025.11270671","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 32nd IEEE International Conference on Electronics, Circuits and Systems (ICECS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"Hossam Mahmoud","orcid":null},"institutions":[{"id":"https://openalex.org/I107720978","display_name":"Ain Shams University","ror":"https://ror.org/00cb9w016","country_code":"EG","type":"education","lineage":["https://openalex.org/I107720978"]}],"countries":["EG"],"is_corresponding":true,"raw_author_name":"Hossam Mahmoud","raw_affiliation_strings":["Ain Shams University,Department of Electronics and Communication Engineering,Cairo,Egypt"],"affiliations":[{"raw_affiliation_string":"Ain Shams University,Department of Electronics and Communication Engineering,Cairo,Egypt","institution_ids":["https://openalex.org/I107720978"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061566407","display_name":"Sameh A. Ibrahim","orcid":"https://orcid.org/0000-0001-8049-1441"},"institutions":[{"id":"https://openalex.org/I107720978","display_name":"Ain Shams University","ror":"https://ror.org/00cb9w016","country_code":"EG","type":"education","lineage":["https://openalex.org/I107720978"]}],"countries":["EG"],"is_corresponding":false,"raw_author_name":"Sameh Ibrahim","raw_affiliation_strings":["Ain Shams University,Department of Electronics and Communication Engineering,Cairo,Egypt"],"affiliations":[{"raw_affiliation_string":"Ain Shams University,Department of Electronics and Communication Engineering,Cairo,Egypt","institution_ids":["https://openalex.org/I107720978"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5060592491","display_name":"Dina El-Damak","orcid":"https://orcid.org/0000-0001-7530-498X"},"institutions":[{"id":"https://openalex.org/I96823368","display_name":"German University in Cairo","ror":"https://ror.org/03rjt0z37","country_code":"EG","type":"education","lineage":["https://openalex.org/I96823368"]}],"countries":["EG"],"is_corresponding":false,"raw_author_name":"Dina El-Damak","raw_affiliation_strings":["German University in Cairo,Department of Electronics and Communication Engineering,Cairo,Egypt"],"affiliations":[{"raw_affiliation_string":"German University in Cairo,Department of Electronics and Communication Engineering,Cairo,Egypt","institution_ids":["https://openalex.org/I96823368"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I107720978"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.38034863,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.4345000088214874,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.4345000088214874,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.23250000178813934,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.14650000631809235,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/wireline","display_name":"Wireline","score":0.8241000175476074},{"id":"https://openalex.org/keywords/linearity","display_name":"Linearity","score":0.7811999917030334},{"id":"https://openalex.org/keywords/differential-nonlinearity","display_name":"Differential nonlinearity","score":0.6104000210762024},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.44589999318122864},{"id":"https://openalex.org/keywords/phase","display_name":"Phase (matter)","score":0.4345000088214874},{"id":"https://openalex.org/keywords/linear-phase","display_name":"Linear phase","score":0.42320001125335693},{"id":"https://openalex.org/keywords/direct-digital-synthesizer","display_name":"Direct digital synthesizer","score":0.421099990606308},{"id":"https://openalex.org/keywords/phase-response","display_name":"Phase response","score":0.3458000123500824},{"id":"https://openalex.org/keywords/quadrature","display_name":"Quadrature (astronomy)","score":0.3255999982357025}],"concepts":[{"id":"https://openalex.org/C2776951270","wikidata":"https://www.wikidata.org/wiki/Q8026910","display_name":"Wireline","level":3,"score":0.8241000175476074},{"id":"https://openalex.org/C77170095","wikidata":"https://www.wikidata.org/wiki/Q1753188","display_name":"Linearity","level":2,"score":0.7811999917030334},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.6180999875068665},{"id":"https://openalex.org/C71217194","wikidata":"https://www.wikidata.org/wiki/Q575958","display_name":"Differential nonlinearity","level":3,"score":0.6104000210762024},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.44589999318122864},{"id":"https://openalex.org/C44280652","wikidata":"https://www.wikidata.org/wiki/Q104837","display_name":"Phase (matter)","level":2,"score":0.4345000088214874},{"id":"https://openalex.org/C20610874","wikidata":"https://www.wikidata.org/wiki/Q512136","display_name":"Linear phase","level":3,"score":0.42320001125335693},{"id":"https://openalex.org/C166089067","wikidata":"https://www.wikidata.org/wiki/Q1227465","display_name":"Direct digital synthesizer","level":5,"score":0.421099990606308},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3910999894142151},{"id":"https://openalex.org/C54767332","wikidata":"https://www.wikidata.org/wiki/Q1751572","display_name":"Phase response","level":3,"score":0.3458000123500824},{"id":"https://openalex.org/C62869609","wikidata":"https://www.wikidata.org/wiki/Q28137","display_name":"Quadrature (astronomy)","level":2,"score":0.3255999982357025},{"id":"https://openalex.org/C158622935","wikidata":"https://www.wikidata.org/wiki/Q660848","display_name":"Nonlinear system","level":2,"score":0.3224000036716461},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.31540000438690186},{"id":"https://openalex.org/C201374245","wikidata":"https://www.wikidata.org/wiki/Q104534","display_name":"Digital subscriber line","level":2,"score":0.31529998779296875},{"id":"https://openalex.org/C137800194","wikidata":"https://www.wikidata.org/wiki/Q11713455","display_name":"Interpolation (computer graphics)","level":3,"score":0.3133000135421753},{"id":"https://openalex.org/C197424946","wikidata":"https://www.wikidata.org/wiki/Q1165717","display_name":"Waveform","level":3,"score":0.3100999891757965},{"id":"https://openalex.org/C761482","wikidata":"https://www.wikidata.org/wiki/Q118093","display_name":"Transmission (telecommunications)","level":2,"score":0.2971999943256378},{"id":"https://openalex.org/C19118579","wikidata":"https://www.wikidata.org/wiki/Q786423","display_name":"Frequency domain","level":2,"score":0.296999990940094},{"id":"https://openalex.org/C47446073","wikidata":"https://www.wikidata.org/wiki/Q5165890","display_name":"Control theory (sociology)","level":3,"score":0.2937999963760376},{"id":"https://openalex.org/C123792056","wikidata":"https://www.wikidata.org/wiki/Q365988","display_name":"Group delay and phase delay","level":3,"score":0.28450000286102295},{"id":"https://openalex.org/C110086884","wikidata":"https://www.wikidata.org/wiki/Q2085341","display_name":"Phase detector","level":3,"score":0.2678999900817871},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.2669000029563904},{"id":"https://openalex.org/C11190779","wikidata":"https://www.wikidata.org/wiki/Q664575","display_name":"Inverter","level":3,"score":0.26649999618530273},{"id":"https://openalex.org/C57747864","wikidata":"https://www.wikidata.org/wiki/Q7180948","display_name":"Phase distortion","level":3,"score":0.2653999924659729},{"id":"https://openalex.org/C207912722","wikidata":"https://www.wikidata.org/wiki/Q1259123","display_name":"Signal generator","level":3,"score":0.26489999890327454},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.26339998841285706},{"id":"https://openalex.org/C74982907","wikidata":"https://www.wikidata.org/wiki/Q1455624","display_name":"Frequency divider","level":3,"score":0.2605000138282776},{"id":"https://openalex.org/C182099602","wikidata":"https://www.wikidata.org/wiki/Q2660678","display_name":"Frequency synthesizer","level":4,"score":0.2529999911785126}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icecs66544.2025.11270671","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs66544.2025.11270671","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 32nd IEEE International Conference on Electronics, Circuits and Systems (ICECS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W880060000","https://openalex.org/W1548579702","https://openalex.org/W1991961966","https://openalex.org/W2024174129","https://openalex.org/W2043454922","https://openalex.org/W2057532062","https://openalex.org/W2072937223","https://openalex.org/W2084894221","https://openalex.org/W2136040141","https://openalex.org/W2790961995","https://openalex.org/W2795622418","https://openalex.org/W2950199094","https://openalex.org/W2962846423","https://openalex.org/W3145305718","https://openalex.org/W3214185915","https://openalex.org/W4226300369","https://openalex.org/W4321484140","https://openalex.org/W4388739316"],"related_works":[],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,54],"4-bit,":[4],"8-phase":[5],"voltage-mode":[6],"phase":[7,38,52],"interpolator":[8],"(PI)":[9],"operating":[10],"at":[11],"5":[12],"GHz":[13],"for":[14,51,57,64,101],"clock":[15],"generation":[16],"in":[17,68],"wireline":[18,103],"transmitters.":[19],"A":[20],"quadrature":[21],"frequency":[22],"divider":[23],"utilizing":[24],"inverter-based":[25],"latches":[26],"with":[27,78],"transmission":[28,62],"gates":[29,63],"generates":[30],"eight":[31],"uniformly":[32],"spaced":[33],"input":[34],"phases":[35],"to":[36],"enhance":[37],"linearity":[39,76],"and":[40,61,85],"timing":[41],"resolution.":[42],"The":[43],"proposed":[44],"PI":[45],"architecture":[46],"comprises":[47],"an":[48],"inverter":[49],"array":[50],"blending,":[53],"digital":[55],"decoder":[56],"interpolation":[58],"weight":[59],"selection,":[60],"quadrant":[65],"selection.":[66],"Implemented":[67],"65-nm":[69],"CMOS":[70],"technology,":[71],"the":[72],"design":[73],"achieves":[74],"superior":[75],"performance":[77],"differential":[79],"nonlin-earity":[80],"(DNL)":[81],"of":[82,89],"0.11":[83],"LSB":[84],"integral":[86],"nonlinearity":[87],"(INL)":[88],"0.29":[90],"LSB,":[91],"while":[92],"consuming":[93],"only":[94],"11.7":[95],"mW":[96],"power,":[97],"making":[98],"it":[99],"well-suited":[100],"high-speed":[102],"communication":[104],"applications.":[105]},"counts_by_year":[],"updated_date":"2026-04-17T18:11:37.981687","created_date":"2025-12-09T00:00:00"}